Vergil_Wong/lib_xua
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Add sw_pll dep and prepare for par in clockgen

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Ed
2024-01-03 15:56:15 +00:00
parent f035e1dc13
commit 2133598347
2 changed files with 457 additions and 443 deletions
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3
lib_xua/module_build_info
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@@ -14,7 +14,8 @@ DEPENDENT_MODULES = lib_locks(>=2.1.0) \
lib_spdif(>=5.0.0) \
lib_xassert(>=4.1.0) \
lib_xud(>=2.2.3) \
lib_adat(>=1.0.0)
lib_adat(>=1.0.0) \
lib_sw_pll(>=2.0.1)
MODULE_XCC_FLAGS = $(XCC_FLAGS) \
-O3 \

17
lib_xua/src/core/clocking/clockgen.xc
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@@ -8,6 +8,13 @@
#include "xua_commands.h"
#include "xua_clocking.h"
#ifdef __XS3A__
extern "C"
{
#include "sw_pll.h"
}
#endif
#if (XUA_SPDIF_RX_EN)
#include "spdif.h"
#endif
@@ -333,6 +340,7 @@ void clockGen (streaming chanend ?c_spdif_rx, chanend ?c_adat_rx, client interfa
/* Initial ref clock output and get timestamp */
i_pll_ref.init();
{
while(1)
{
select
@@ -452,6 +460,8 @@ void clockGen (streaming chanend ?c_spdif_rx, chanend ?c_adat_rx, client interfa
/* Setup next local clock edge */
i_pll_ref.toggle_timed(0);
printstr("d\n");
/* Record time of edge */
timeLastEdge = timeNextEdge;
@@ -574,6 +584,7 @@ void clockGen (streaming chanend ?c_spdif_rx, chanend ?c_adat_rx, client interfa
/* Toggle edge */
i_pll_ref.toggle_timed(1);
printstr("s\n");
/* Reset counters */
spdifCounters.receivedSamples = 0;
@@ -680,6 +691,7 @@ void clockGen (streaming chanend ?c_spdif_rx, chanend ?c_adat_rx, client interfa
/* Toggle edge */
i_pll_ref.toggle_timed(1);
printstr("a\n");
/* Reset counters */
adatCounters.receivedSamples = 0;
@@ -816,7 +828,8 @@ void clockGen (streaming chanend ?c_spdif_rx, chanend ?c_adat_rx, client interfa
outuint(c_dig_rx, 1);
break;
#endif
}
}
} /* select */
} /* while(1) */
} /* clkgen task scope */
}