Output functional in simple app. Issue at high volume. Still uses sc_i2c.
This commit is contained in:
xross
@@ -8,7 +8,8 @@ XCC_FLAGS = -fcomment-asm -Xmapper --map -Xmapper MAPFILE -O3 -report -fsubw
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# The USED_MODULES variable lists other module used by the application. These
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# modules will extend the SOURCE_DIRS, INCLUDE_DIRS and LIB_DIRS variables.
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# Modules are expected to be in the directory above the BASE_DIR directory.
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USED_MODULES = lib_i2c lib_mic_array lib_logging lib_xua lib_device_control lib_src lib_dsp lib_spi lib_xud
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USED_MODULES = lib_mic_array lib_logging lib_xua lib_device_control lib_xud module_i2c_shared module_i2c_single_port module_locks
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#=============================================================================
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# The following part of the Makefile includes the common build infrastructure
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@@ -1,8 +1,12 @@
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/* A very simple example of a USB audio application (and as such is un-verified)
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*
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/* A very simple *example* of a USB audio application (and as such is un-verified for production)
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*
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* It uses the main blocks from the lib_xua
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*
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* - 2 in/ 2 out I2S only
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* - No DFU
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* - I2S only
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*
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*/
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#include <xs1.h>
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@@ -11,26 +15,21 @@
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#include "xud_device.h"
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#include "xua.h"
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/* Ports - note the defines come from the xn file */
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/* Port declarations. Note, the defines come from the xn file */
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buffered out port:32 p_i2s_dac[] = {PORT_I2S_DAC0}; /* I2S Data-line(s) */
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buffered out port:32 p_lrclk = PORT_I2S_LRCLK; /* I2S Bit-clock */
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buffered out port:32 p_bclk = PORT_I2S_BCLK; /* I2S L/R-clock */
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/* I2S ports - Data-line, bit-clock and L/R clock */
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buffered out port:32 p_i2s_dac[] = {PORT_I2S_DAC0};
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buffered out port:32 p_lrclk = PORT_I2S_LRCLK;
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buffered out port:32 p_bclk = PORT_I2S_BCLK;
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port p_mclk_in = PORT_MCLK_IN; /* Audio master clock input */
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/* Audio master-clock port */
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port p_mclk_in = PORT_MCLK_IN;
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in port p_for_mclk_count = PORT_MCLK_COUNT; /* Extra port for counting master clock ticks */
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/* Port for counting master clocks */
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in port p_for_mclk_count = PORT_MCLK_COUNT;
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/* Clock-blocks for master-clock and bit-clock */
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clock clk_audio_bclk = on tile[0]: XS1_CLKBLK_4;
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clock clk_audio_mclk = on tile[0]: XS1_CLKBLK_5;
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/* Clock-block declarations */
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clock clk_audio_bclk = on tile[0]: XS1_CLKBLK_4; /* Bit clock */
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clock clk_audio_mclk = on tile[0]: XS1_CLKBLK_5; /* Master clock */
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/* Endpoint type tables - informs XUD what the transfer types for each Endpoint in use and also
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* if the endpoint wishes to be informed of USB bus resets
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*/
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* if the endpoint wishes to be informed of USB bus resets */
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XUD_EpType epTypeTableOut[] = {XUD_EPTYPE_CTL | XUD_STATUS_ENABLE, XUD_EPTYPE_ISO};
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XUD_EpType epTypeTableIn[] = {XUD_EPTYPE_CTL | XUD_STATUS_ENABLE, XUD_EPTYPE_ISO};
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@@ -40,13 +39,18 @@ int main()
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chan c_ep_out[2];
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chan c_ep_in[2];
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/* TODO handle this */
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chan c_aud_ctl;
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/* Channel for communicating SOF notifications from XUD to the Buffering cores */
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chan c_sof;
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/* Channel for audio data between buffering cores and audio IO core */
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chan c_aud;
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/* Channel for communcating control messages from EP0 to the rest of the device (via the buffering cores */
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chan c_aud_ctl;
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/* TODO handle this */
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interface audManage_if i_audMan;
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par
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{
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@@ -61,31 +65,13 @@ int main()
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/* Note, since we are not using many features we pass in null for quite a few params.. */
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on tile[1]: XUA_Endpoint0(c_ep_out[0], c_ep_in[0], c_aud_ctl, null, null, null, null);
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/* Buffering cores - handles audio data to/from EP's and gives/gets data from the audio I/O core */
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/* Buffering cores - handles audio data to/from EP's and gives/gets data to/from the audio I/O core */
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/* Note, this spawns two cores */
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on tile[1]: XUA_Buffer(c_ep_out[1], c_ep_in[1], c_sof, c_aud_ctl, p_for_mclk_count, c_aud);
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#if 0
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/* Audio I/o core i.e. I2S */
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on tile[1]: audio(AUDIO_CHANNEL,
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#if defined(SPDIF_TX) && (SPDIF_TX_TILE != AUDIO_IO_TILE)
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c_spdif_tx,
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#endif
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#if defined(SPDIF_RX) || defined(ADAT_RX)
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c_dig_rx,
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#endif
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c_aud_cfg, c_adc
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#if (XUD_TILE != 0) && (AUDIO_IO_TILE == 0)
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, dfuInterface
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#endif
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#if (NUM_PDM_MICS > 0)
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, c_pdm_pcm
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#endif
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, i_audMan
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);
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#endif
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}
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/* IOHub core does most of the audio IO i.e. I2S (also serves as a hub for all audio) */
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on tile[0]: XUA_AudioHub(c_aud, i_audMan);
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}
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return 0;
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}
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31
examples/app_xua_simple/src/cs4384.h
Normal file
31
examples/app_xua_simple/src/cs4384.h
Normal file
@@ -0,0 +1,31 @@
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#ifndef CS4384_H_
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#define CS4384_H_
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//Address on I2C bus
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#define CS4384_I2C_ADDR (0x18)
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//Register Addresess
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#define CS4384_CHIP_REV 0x01
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#define CS4384_MODE_CTRL 0x02
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#define CS4384_PCM_CTRL 0x03
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#define CS4384_DSD_CTRL 0x04
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#define CS4384_FLT_CTRL 0x05
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#define CS4384_INV_CTRL 0x06
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#define CS4384_GRP_CTRL 0x07
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#define CS4384_RMP_MUTE 0x08
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#define CS4384_MUTE_CTRL 0x09
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#define CS4384_MIX_PR1 0x0a
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#define CS4384_VOL_A1 0x0b
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#define CS4384_VOL_B1 0x0c
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#define CS4384_MIX_PR2 0x0d
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#define CS4384_VOL_A2 0x0e
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#define CS4384_VOL_B2 0x0f
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#define CS4384_MIX_PR3 0x10
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#define CS4384_VOL_A3 0x11
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#define CS4384_VOL_B3 0x12
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#define CS4384_MIX_PR4 0x13
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#define CS4384_VOL_A4 0x14
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#define CS4384_VOL_B4 0x15
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#define CS4384_CM_MODE 0x16
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#endif /* CS4384_H_ */
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17
examples/app_xua_simple/src/cs5368.h
Normal file
17
examples/app_xua_simple/src/cs5368.h
Normal file
@@ -0,0 +1,17 @@
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#ifndef _CS5368_H_
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#define _CS5368_H_
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//Address on I2C bus
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#define CS5368_I2C_ADDR (0x4C)
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//Register Addresess
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#define CS5368_CHIP_REV 0x00
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#define CS5368_GCTL_MDE 0x01
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#define CS5368_OVFL_ST 0x02
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#define CS5368_OVFL_MSK 0x03
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#define CS5368_HPF_CTRL 0x04
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#define CS5368_PWR_DN 0x06
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#define CS5368_MUTE_CTRL 0x08
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#define CS5368_SDO_EN 0x0a
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#endif /* _CS5368_H_ */
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@@ -21,8 +21,8 @@
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#define SPDIF_TX_INDEX 0
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#define VENDOR_STR "XMOS"
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#define VENDOR_ID 0x20B1
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#define PRODUCT_STR_A2 "XUA Simple"
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#define PRODUCT_STR_A1 "XUA Simple"
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#define PRODUCT_STR_A2 "XUA Example"
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#define PRODUCT_STR_A1 "XUA Example"
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#define PID_AUDIO_1 1
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#define PID_AUDIO_2 2
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#define AUDIO_CLASS 2
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@@ -1,50 +0,0 @@
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#include "gpio_access.h"
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//#include "swlock.h"
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#include <xs1.h>
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//swlock_t gpo_swlock = SWLOCK_INITIAL_VALUE;
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void p_gpio_lock()
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{
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//swlock_acquire(&gpo_swlock);
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}
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void p_gpio_unlock()
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{
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//swlock_release(&gpo_swlock);
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}
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unsigned p_gpio_peek()
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{
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unsigned portId, x;
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// Wrapped in lock to ensure it's safe from multiple logical cores
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// swlock_acquire(&gpo_swlock);
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asm("ldw %0, dp[p_gpio]":"=r"(portId));
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asm volatile("peek %0, res[%1]":"=r"(x):"r"(portId));
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return x;
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}
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void p_gpio_out(unsigned x)
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{
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unsigned portId;
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asm("ldw %0, dp[p_gpio]":"=r"(portId));
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asm volatile("out res[%0], %1"::"r"(portId),"r"(x));
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// Wrapped in lock to ensure it's safe from multiple logical cores
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//swlock_release(&gpo_swlock);
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}
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void set_gpio(unsigned bit, unsigned value)
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{
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unsigned port_shadow;
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port_shadow = p_gpio_peek(); // Read port pin value
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if (value == 0) port_shadow &= ~bit; // If writing a 0, generate mask and AND with current val
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else port_shadow |= bit; // Else use mask and OR to set bit
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p_gpio_out(port_shadow); // Write back to port. Will make port an output if not already
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}
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@@ -1,51 +0,0 @@
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#ifndef _GPIO_ACCESS_H_
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#define _GPIO_ACCESS_H_
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#include "customdefines.h"
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#if XCORE_200_MC_AUDIO_HW_VERSION == 2
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/* General output port bit definitions */
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#define P_GPIO_DSD_MODE (1 << 0) /* DSD mode select 0 = 8i/8o I2S, 1 = 8o DSD*/
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#define P_GPIO_DAC_RST_N (1 << 1)
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#define P_GPIO_USB_SEL0 (1 << 2)
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#define P_GPIO_USB_SEL1 (1 << 3)
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#define P_GPIO_VBUS_EN (1 << 4)
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#define P_GPIO_PLL_SEL (1 << 5) /* 1 = CS2100, 0 = Phaselink clock source */
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#define P_GPIO_ADC_RST_N (1 << 6)
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#define P_GPIO_MCLK_FSEL (1 << 7) /* Select frequency on Phaselink clock. 0 = 24.576MHz for 48k, 1 = 22.5792MHz for 44.1k.*/
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#else
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/* General output port bit definitions */
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#define P_GPIO_DSD_MODE (1 << 0) /* DSD mode select 0 = 8i/8o I2S, 1 = 8o DSD*/
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#define P_GPIO_DAC_RST_N (1 << 1)
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#define P_GPIO_ADC_RST_N (1 << 2)
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#define P_GPIO_USB_SEL0 (1 << 3)
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#define P_GPIO_USB_SEL1 (1 << 4)
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#define P_GPIO_VBUS_EN (1 << 5)
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#define P_GPIO_MCLK_FSEL (1 << 6) /* Select frequency on Phaselink clock. 0 = 24.576MHz for 48k, 1 = 22.5792MHz for 44.1k.*/
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#define P_GPIO_PLL_SEL (1 << 7) /* 1 = CS2100, 0 = Phaselink clock source */
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#endif
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/*LED array defines*/
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#define LED_ALL_ON 0xf00f
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#define LED_SQUARE_BIG 0x9009
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#define LED_SQUARE_SML 0x6006
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#define LED_ROW_1 0xf001
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#define LED_ROW_2 0xf003
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#define LED_ROW_3 0xf007
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#define ALL_OFF 0x0000
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// LED array masks
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#define LED_MASK_COL_OFF 0x7fff
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#define LED_MASK_DISABLE 0xffff
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void set_gpio(unsigned bit, unsigned value);
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void p_gpio_lock();
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void p_gpio_unlock();
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unsigned p_gpio_peek();
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void p_gpio_out(unsigned x);
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#endif
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@@ -1,20 +1,135 @@
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// Copyright (c) 2016, XMOS Ltd, All rights reserved
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#include <platform.h>
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#include <timer.h>
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#include "audiohw.h"
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#include "customdefines.h"
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#include "gpio_access.h"
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#include "i2c_shared.h"
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#include "cs5368.h"
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#include "cs4384.h"
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on tile [0] : struct r_i2c r_i2c = {XS1_PORT_4A};
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void AudioHwConfig(unsigned samFreq, unsigned mClk, chanend ?c_codec, unsigned dsdMode,
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/* General output port bit definitions */
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#define P_GPIO_DSD_MODE (1 << 0) /* DSD mode select 0 = 8i/8o I2S, 1 = 8o DSD*/
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#define P_GPIO_DAC_RST_N (1 << 1)
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#define P_GPIO_USB_SEL0 (1 << 2)
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#define P_GPIO_USB_SEL1 (1 << 3)
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#define P_GPIO_VBUS_EN (1 << 4)
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#define P_GPIO_PLL_SEL (1 << 5) /* 1 = CS2100, 0 = Phaselink clock source */
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#define P_GPIO_ADC_RST_N (1 << 6)
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#define P_GPIO_MCLK_FSEL (1 << 7) /* Select frequency on Phaselink clock. 0 = 24.576MHz for 48k, 1 = 22.5792MHz for 44.1k.*/
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#define DAC_REGWRITE(reg, val) {data[0] = val; i2c_shared_master_write_reg(r_i2c, CS4384_I2C_ADDR, reg, data, 1);}
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#define DAC_REGREAD(reg, val) {i2c_shared_master_read_reg(r_i2c, CS4384_I2C_ADDR, reg, val, 1);}
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#define ADC_REGWRITE(reg, val) {data[0] = val; i2c_shared_master_write_reg(r_i2c, CS5368_I2C_ADDR, reg, data, 1);}
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out port p_gpio = on tile[0]:XS1_PORT_8C;
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void AudioHwConfig(unsigned samFreq, unsigned mClk, unsigned dsdMode,
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unsigned sampRes_DAC, unsigned sampRes_ADC)
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{
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// nothing
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unsigned char data[1] = {0};
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unsigned char gpioVal = 0;
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/* Set master clock select appropriately and put ADC and DAC into reset */
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if (mClk == MCLK_441)
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{
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gpioVal = P_GPIO_USB_SEL0 | P_GPIO_USB_SEL1;
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}
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else
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{
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gpioVal = P_GPIO_USB_SEL0 | P_GPIO_USB_SEL1 | P_GPIO_MCLK_FSEL;
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}
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p_gpio <: gpioVal;
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/* Allow MCLK to settle */
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delay_microseconds(20000);
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/* Take ADC out of reset */
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gpioVal |= P_GPIO_ADC_RST_N;
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p_gpio <: gpioVal;
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/* Configure ADC for I2S slave mode via I2C */
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unsigned dif = 0, mode = 0;
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dif = 0x01; /* I2S */
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mode = 0x03; /* Slave mode all speeds */
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/* Reg 0x01: (GCTL) Global Mode Control Register
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* Bit[7]: CP-EN: Manages control-port mode
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* Bit[6]: CLKMODE: Setting puts part in 384x mode
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* Bit[5:4]: MDIV[1:0]: Set to 01 for /2
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* Bit[3:2]: DIF[1:0]: Data Format: 0x01 for I2S, 0x02 for TDM
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* Bit[1:0]: MODE[1:0]: Mode: 0x11 for slave mode
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*/
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ADC_REGWRITE(CS5368_GCTL_MDE, 0b10010000 | (dif << 2) | mode);
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/* Reg 0x06: (PDN) Power Down Register */
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/* Bit[7:6]: Reserved
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* Bit[5]: PDN-BG: When set, this bit powers-own the bandgap reference
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* Bit[4]: PDM-OSC: Controls power to internal oscillator core
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* Bit[3:0]: PDN: When any bit is set all clocks going to that channel pair are turned off
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*/
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ADC_REGWRITE(CS5368_PWR_DN, 0b00000000);
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/* Configure DAC with PCM values. Note 2 writes to mode control to enable/disable freeze/power down */
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/* Take DAC out of reset */
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gpioVal |= P_GPIO_DAC_RST_N;
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p_gpio <: gpioVal;
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delay_microseconds(500);
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/* Mode Control 1 (Address: 0x02) */
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/* bit[7] : Control Port Enable (CPEN) : Set to 1 for enable
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* bit[6] : Freeze controls (FREEZE) : Set to 1 for freeze
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* bit[5] : PCM/DSD Selection (DSD/PCM) : Set to 0 for PCM
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* bit[4:1] : DAC Pair Disable (DACx_DIS) : All Dac Pairs enabled
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* bit[0] : Power Down (PDN) : Powered down
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*/
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DAC_REGWRITE(CS4384_MODE_CTRL, 0b11000001);
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/* PCM Control (Address: 0x03) */
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/* bit[7:4] : Digital Interface Format (DIF) : 0b0001 for I2S up to 24bit
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* bit[3:2] : Reserved
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* bit[1:0] : Functional Mode (FM) : 0x00 - single-speed mode (4-50kHz)
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* : 0x01 - double-speed mode (50-100kHz)
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* : 0x10 - quad-speed mode (100-200kHz)
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* : 0x11 - auto-speed detect (32 to 200kHz)
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* (note, some Mclk/SR ratios not supported in auto)
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*
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*/
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unsigned char regVal = 0;
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if(samFreq < 50000)
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regVal = 0b00010100;
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else if(samFreq < 100000)
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regVal = 0b00010101;
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else //if(samFreq < 200000)
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regVal = 0b00010110;
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DAC_REGWRITE(CS4384_PCM_CTRL, regVal);
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/* Mode Control 1 (Address: 0x02) */
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/* bit[7] : Control Port Enable (CPEN) : Set to 1 for enable
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* bit[6] : Freeze controls (FREEZE) : Set to 0 for freeze
|
||||
* bit[5] : PCM/DSD Selection (DSD/PCM) : Set to 0 for PCM
|
||||
* bit[4:1] : DAC Pair Disable (DACx_DIS) : All Dac Pairs enabled
|
||||
* bit[0] : Power Down (PDN) : Not powered down
|
||||
*/
|
||||
DAC_REGWRITE(CS4384_MODE_CTRL, 0b10000000);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void AudioHwInit(chanend ?c_codec)
|
||||
void AudioHwInit()
|
||||
{
|
||||
set_gpio(P_GPIO_USB_SEL0, 1);
|
||||
set_gpio(P_GPIO_USB_SEL1, 1);
|
||||
/* Set USB Mux to micro-b */
|
||||
/* ADC and DAC in reset */
|
||||
p_gpio <: P_GPIO_USB_SEL0 | P_GPIO_USB_SEL1;
|
||||
|
||||
/* Init the i2c module */
|
||||
i2c_shared_master_init(r_i2c);
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user