Vergil_Wong/lib_xua
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Master clock used to clock bit-clock clock-block directly when BCLK==MCLK. This improves I2S timing (esp at 384kHz when MCLK=24.576Mhz..)

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Ross Owen
2014-04-25 12:28:09 +01:00
parent 9b6ce98cbe
commit 3a74a38638
1 changed files with 7 additions and 4 deletions
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5
module_usb_audio/ports/audioports.xc
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@@ -65,15 +65,18 @@ unsigned int divide)
if (divide == 1) /* e.g. 176.4KHz from 11.2896 */ if (divide == 1) /* e.g. 176.4KHz from 11.2896 */
{ {
configure_port_clock_output(p_bclk, clk_audio_mclk); configure_port_clock_output(p_bclk, clk_audio_mclk);
/* Generate bit clock block straight from mclk */
configure_clock_src(clk_audio_bclk, p_mclk_in);
} }
else else
{ {
/* bit clock port from master clock clock-clock block */ /* bit clock port from master clock clock-clock block */
configure_out_port_no_ready(p_bclk, clk_audio_mclk, 0); configure_out_port_no_ready(p_bclk, clk_audio_mclk, 0);
}
/* Generate bit clock block from pin */ /* Generate bit clock block from pin */
configure_clock_src(clk_audio_bclk, p_bclk); configure_clock_src(clk_audio_bclk, p_bclk);
}
if(!isnull(p_lrclk)) if(!isnull(p_lrclk))
{ {