* Renamed test_sync to test_sync_clk_basic

* Authored test for known issue in sync mode, test_sync_clk_plugin
* Removed some unrequired test related files

tests/test_sync_clk_basic/Makefile

@@ -0,0 +1,11 @@
+
+TEST_FLAGS ?=
+
+XCC_FLAGS = -O3 -g -DXUD_CORE_CLOCK=600 -save-temps -DUSB_TILE=tile[0] -DLOCAL_CLOCK_INCREMENT=10000 -DLOCAL_CLOCK_MARGIN=100 $(TEST_FLAGS)
+
+TARGET = test_xs3_600.xn
+
+USED_MODULES = lib_xua
+
+XMOS_MAKE_PATH ?= ../..
+-include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common

tests/test_sync_clk_basic/src/main.xc

@@ -0,0 +1,167 @@
+// Copyright 2022 XMOS LIMITED.
+// This Software is subject to the terms of the XMOS Public Licence: Version 1.
+
+/* Simples test to ensure reference clock to CS2100 device continues when SOF clock not available
+ * Note, this test uses "nice" numbers and it doesn't check for graceful change over from internal to SOF clock 
+ */
+
+#include "platform.h"
+#include "xua.h"
+#include "uac_hwresources.h"
+#include "print.h"
+
+#define EP_COUNT_IN 3
+#define EP_COUNT_OUT 3
+
+out port p_pll_ref               = XS1_PORT_1A; 
+in port p_off_mclk               = XS1_PORT_1M;
+in port p_pll_loop               = XS1_PORT_1B; /* Note, this is externally looped back using the loopback plugin */
+
+/* Purely for debug/viewing on VCD */
+out port p_test                  = XS1_PORT_1C;
+
+/* To speed this test up we divide all delays by 10. This is also the case for the delays in the clock generation code */
+#define SOF_PERIOD_TICKS   (12500/10)
+
+#ifndef MISSING_SOFS
+#define MISSING SOFS (8)
+#endif
+
+void exit(int);
+
+void delay(unsigned d)
+{
+    timer t;
+    unsigned time;
+    t :> time;
+    t when timerafter(time + d) :> int x;
+}  
+
+/* From lib_xud */
+void SetupEndpoints(chanend c_ep_out[], int noEpOut, chanend c_ep_in[], int noEpIn, XUD_EpType epTypeTableOut[], XUD_EpType epTypeTableIn[]);
+
+void AudioHwInit()
+{
+    return;
+}
+
+void AudioHwConfig(unsigned samFreq, unsigned mClk, unsigned dsdMode,
+    unsigned sampRes_DAC, unsigned sampRes_ADC)
+{
+    return;
+}
+
+void driveSofs(chanend c_sof, int count)
+{
+    static int sof = 0;
+    for(int i = 0; i < count; i++)
+    {
+        outuint(c_sof, sof++);
+        delay(SOF_PERIOD_TICKS);
+    }
+}
+
+void fake_xud(chanend c_out[], chanend c_in[], chanend c_sof)
+{
+    timer t;
+    unsigned time;
+  
+    p_test <: 1;
+
+    /* Makes traces a bit nicer to look at */ 
+    t :> time;
+    t when timerafter(SOF_PERIOD_TICKS * 2) :> int x;
+   
+    /* Endpoint type tables */
+    XUD_EpType epTypeTableOut[EP_COUNT_OUT] = {XUD_EPTYPE_CTL, XUD_EPTYPE_ISO, XUD_EPTYPE_DIS};
+    XUD_EpType epTypeTableIn[EP_COUNT_IN] =   {XUD_EPTYPE_CTL, XUD_EPTYPE_ISO, XUD_EPTYPE_ISO};
+ 
+    SetupEndpoints(c_out, EP_COUNT_OUT, c_in, EP_COUNT_IN, epTypeTableOut, epTypeTableIn);
+
+    driveSofs(c_sof, 32);
+     
+    p_test <: 0;
+    
+    /* Sim missing SOFs */   
+    delay(SOF_PERIOD_TICKS*MISSING_SOFS);
+    
+    p_test <: 1;
+    
+    driveSofs(c_sof, 16);
+    
+    p_test <: 0;
+}
+
+extern XUD_BusSpeed_t g_curUsbSpeed;
+
+#define MARGIN (1500/10)
+#define EXPECTED_PERIOD (100000/10) // Test runs as HS - so 8 * 125000
+
+void checker()
+{
+    timer t; 
+    unsigned t0, t1;
+    unsigned x = 0;
+
+    int fail = 0;
+
+    p_pll_loop when pinseq(1) :> x;
+    p_pll_loop when pinseq(0) :> x;
+    p_pll_loop when pinseq(1) :> x;
+
+    for(int i = 0; i < 8; i++)
+    {
+        p_pll_loop when pinsneq(x) :>  x;
+        t :> t0;
+        p_pll_loop when pinsneq(x) :>  x;
+        t :> t1;
+   
+        int period = t1-t0;
+
+        /* Check the period of the reference clock we are generating */
+        if(period > (EXPECTED_PERIOD + MARGIN))
+        {
+            printstr("Period too long: ");
+            printintln(period);
+            fail = 1;
+        }
+        else if(period < (EXPECTED_PERIOD - MARGIN))
+        {
+            printstr("Period too short: ");
+            printintln(period);
+            fail = 1;
+        }
+    }
+    if(!fail)
+        printstrln("PASS");
+
+    exit(0);
+}
+
+
+int main()
+{
+    chan c_out[EP_COUNT_OUT];
+    chan c_in[EP_COUNT_IN];
+    chan c_sof;
+    chan c_aud_ctl;
+
+    interface pll_ref_if i_pll_ref;
+
+    par
+    {
+        PllRefPinTask(i_pll_ref, p_pll_ref);
+
+        {
+            g_curUsbSpeed = XUD_SPEED_HS;
+            XUA_Buffer_Ep(c_out[1],      /* USB Audio Out*/
+                c_in[1],                 /* USB Audio In */
+                c_sof, c_aud_ctl, p_off_mclk, i_pll_ref
+            );
+        }
+
+        fake_xud(c_out, c_in, c_sof);
+    
+        checker();
+    }
+}

tests/test_sync_clk_basic/src/test_xs3_600.xn

@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Network xmlns="http://www.xmos.com"
+         xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+         xsi:schemaLocation="http://www.xmos.com http://www.xmos.com">
+  <Declarations>
+    <Declaration>tileref tile[2]</Declaration>
+  </Declarations>
+
+  <Packages>
+    <Package id="0" Type="XS3-UnA-1024-FB265">
+      <Nodes>
+        <Node Id="0" InPackageId="0" Type="XS3-L16A-1024" Oscillator="24MHz" SystemFrequency="600MHz" ReferenceFrequency="100MHz">
+          <Tile Number="0" Reference="tile[0]"/>
+          <Tile Number="1" Reference="tile[1]"/>
+        </Node>
+      </Nodes>
+    </Package>
+  </Packages>
+
+  <JTAGChain>
+    <JTAGDevice NodeId="0"/>
+  </JTAGChain>
+
+</Network>

tests/test_sync_clk_basic/src/xua_conf.h

@@ -0,0 +1,44 @@
+// Copyright 2016-2022 XMOS LIMITED.
+// This Software is subject to the terms of the XMOS Public Licence: Version 1.
+#ifndef _XUA_CONF_H_
+#define _XUA_CONF_H_
+
+#define NUM_USB_CHAN_OUT        (2)
+#define NUM_USB_CHAN_IN         (2)
+#define I2S_CHANS_DAC           (2)
+#define I2S_CHANS_ADC           (2)
+
+#define XUA_SYNCMODE           XUA_SYNCMODE_SYNC
+#define UAC_FORCE_FEEDBACK_EP   (0) 
+
+#define EXCLUDE_USB_AUDIO_MAIN
+#define XUA_NUM_PDM_MICS 0
+#define XUD_TILE 1
+#define AUDIO_IO_TILE 0
+#define MIXER 0
+
+#ifndef MCLK_441
+#define MCLK_441 (512 * 44100)
+#endif
+
+#ifndef MCLK_48
+#define MCLK_48 (512 * 48000)
+#endif
+
+#define MIN_FREQ (44100)
+#define MAX_FREQ (192000)
+#define SPDIF_TX_INDEX 0
+#define VENDOR_STR "XMOS"
+#define VENDOR_ID 0x20B1
+#define PRODUCT_STR_A2 "Test device"
+#define PRODUCT_STR_A1 "Test device"
+#define PID_AUDIO_1 1
+#define PID_AUDIO_2 2
+#define AUDIO_CLASS 2
+#define AUDIO_CLASS_FALLBACK 0
+#define BCD_DEVICE 0x1234
+#define XUA_DFU_EN          0
+#define MIC_DUAL_ENABLED 1        //Use single thread, dual PDM mic
+#define XUA_MIC_FRAME_SIZE 240
+
+#endif