* Renamed test_sync to test_sync_clk_basic
* Authored test for known issue in sync mode, test_sync_clk_plugin * Removed some unrequired test related files
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167
tests/test_sync_clk_basic/src/main.xc
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167
tests/test_sync_clk_basic/src/main.xc
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// Copyright 2022 XMOS LIMITED.
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// This Software is subject to the terms of the XMOS Public Licence: Version 1.
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/* Simples test to ensure reference clock to CS2100 device continues when SOF clock not available
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* Note, this test uses "nice" numbers and it doesn't check for graceful change over from internal to SOF clock
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*/
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#include "platform.h"
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#include "xua.h"
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#include "uac_hwresources.h"
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#include "print.h"
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#define EP_COUNT_IN 3
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#define EP_COUNT_OUT 3
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out port p_pll_ref = XS1_PORT_1A;
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in port p_off_mclk = XS1_PORT_1M;
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in port p_pll_loop = XS1_PORT_1B; /* Note, this is externally looped back using the loopback plugin */
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/* Purely for debug/viewing on VCD */
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out port p_test = XS1_PORT_1C;
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/* To speed this test up we divide all delays by 10. This is also the case for the delays in the clock generation code */
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#define SOF_PERIOD_TICKS (12500/10)
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#ifndef MISSING_SOFS
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#define MISSING SOFS (8)
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#endif
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void exit(int);
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void delay(unsigned d)
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{
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timer t;
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unsigned time;
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t :> time;
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t when timerafter(time + d) :> int x;
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}
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/* From lib_xud */
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void SetupEndpoints(chanend c_ep_out[], int noEpOut, chanend c_ep_in[], int noEpIn, XUD_EpType epTypeTableOut[], XUD_EpType epTypeTableIn[]);
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void AudioHwInit()
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{
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return;
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}
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void AudioHwConfig(unsigned samFreq, unsigned mClk, unsigned dsdMode,
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unsigned sampRes_DAC, unsigned sampRes_ADC)
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{
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return;
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}
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void driveSofs(chanend c_sof, int count)
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{
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static int sof = 0;
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for(int i = 0; i < count; i++)
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{
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outuint(c_sof, sof++);
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delay(SOF_PERIOD_TICKS);
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}
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}
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void fake_xud(chanend c_out[], chanend c_in[], chanend c_sof)
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{
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timer t;
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unsigned time;
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p_test <: 1;
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/* Makes traces a bit nicer to look at */
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t :> time;
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t when timerafter(SOF_PERIOD_TICKS * 2) :> int x;
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/* Endpoint type tables */
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XUD_EpType epTypeTableOut[EP_COUNT_OUT] = {XUD_EPTYPE_CTL, XUD_EPTYPE_ISO, XUD_EPTYPE_DIS};
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XUD_EpType epTypeTableIn[EP_COUNT_IN] = {XUD_EPTYPE_CTL, XUD_EPTYPE_ISO, XUD_EPTYPE_ISO};
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SetupEndpoints(c_out, EP_COUNT_OUT, c_in, EP_COUNT_IN, epTypeTableOut, epTypeTableIn);
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driveSofs(c_sof, 32);
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p_test <: 0;
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/* Sim missing SOFs */
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delay(SOF_PERIOD_TICKS*MISSING_SOFS);
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p_test <: 1;
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driveSofs(c_sof, 16);
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p_test <: 0;
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}
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extern XUD_BusSpeed_t g_curUsbSpeed;
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#define MARGIN (1500/10)
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#define EXPECTED_PERIOD (100000/10) // Test runs as HS - so 8 * 125000
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void checker()
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{
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timer t;
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unsigned t0, t1;
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unsigned x = 0;
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int fail = 0;
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p_pll_loop when pinseq(1) :> x;
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p_pll_loop when pinseq(0) :> x;
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p_pll_loop when pinseq(1) :> x;
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for(int i = 0; i < 8; i++)
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{
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p_pll_loop when pinsneq(x) :> x;
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t :> t0;
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p_pll_loop when pinsneq(x) :> x;
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t :> t1;
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int period = t1-t0;
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/* Check the period of the reference clock we are generating */
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if(period > (EXPECTED_PERIOD + MARGIN))
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{
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printstr("Period too long: ");
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printintln(period);
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fail = 1;
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}
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else if(period < (EXPECTED_PERIOD - MARGIN))
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{
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printstr("Period too short: ");
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printintln(period);
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fail = 1;
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}
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}
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if(!fail)
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printstrln("PASS");
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exit(0);
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}
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int main()
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{
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chan c_out[EP_COUNT_OUT];
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chan c_in[EP_COUNT_IN];
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chan c_sof;
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chan c_aud_ctl;
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interface pll_ref_if i_pll_ref;
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par
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{
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PllRefPinTask(i_pll_ref, p_pll_ref);
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{
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g_curUsbSpeed = XUD_SPEED_HS;
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XUA_Buffer_Ep(c_out[1], /* USB Audio Out*/
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c_in[1], /* USB Audio In */
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c_sof, c_aud_ctl, p_off_mclk, i_pll_ref
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);
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}
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fake_xud(c_out, c_in, c_sof);
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checker();
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}
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}
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