From e6d3c659028476079ec76e2cd6de219208bc4d32 Mon Sep 17 00:00:00 2001 From: xross Date: Thu, 8 Sep 2022 17:45:28 +0100 Subject: [PATCH 1/7] Revert "Updated various vars from unsigned to int in decouple" This reverts commit 9f105dd48a0f81557d0ac1f6d8d9ec0ba9a699a4. --- lib_xua/src/core/buffer/decouple/decouple.xc | 24 ++++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/lib_xua/src/core/buffer/decouple/decouple.xc b/lib_xua/src/core/buffer/decouple/decouple.xc index 085d27cf..60002b35 100644 --- a/lib_xua/src/core/buffer/decouple/decouple.xc +++ b/lib_xua/src/core/buffer/decouple/decouple.xc @@ -65,18 +65,18 @@ static xc_ptr p_multIn; #endif #if (AUDIO_CLASS == 2) -int g_numUsbChan_In = NUM_USB_CHAN_IN; /* Number of channels to/from the USB bus - initialised to HS for UAC2.0 */ -int g_numUsbChan_Out = NUM_USB_CHAN_OUT; -int g_curSubSlot_Out = HS_STREAM_FORMAT_OUTPUT_1_SUBSLOT_BYTES; -int g_curSubSlot_In = HS_STREAM_FORMAT_INPUT_1_SUBSLOT_BYTES; +unsigned g_numUsbChan_In = NUM_USB_CHAN_IN; /* Number of channels to/from the USB bus - initialised to HS for UAC2.0 */ +unsigned g_numUsbChan_Out = NUM_USB_CHAN_OUT; +unsigned g_curSubSlot_Out = HS_STREAM_FORMAT_OUTPUT_1_SUBSLOT_BYTES; +unsigned g_curSubSlot_In = HS_STREAM_FORMAT_INPUT_1_SUBSLOT_BYTES; int sampsToWrite = DEFAULT_FREQ/8000; /* HS assumed here. Expect to be junked during a overflow before stream start */ int totalSampsToWrite = DEFAULT_FREQ/8000; int g_maxPacketSize = MAX_DEVICE_AUD_PACKET_SIZE_IN_HS; /* IN packet size. Init to something sensible, but expect to be re-set before stream start */ #else -int g_numUsbChan_In = NUM_USB_CHAN_IN_FS; /* Number of channels to/from the USB bus - initialised to FS for UAC1.0 */ -int g_numUsbChan_Out = NUM_USB_CHAN_OUT_FS; -int g_curSubSlot_Out = FS_STREAM_FORMAT_OUTPUT_1_SUBSLOT_BYTES; -int g_curSubSlot_In = FS_STREAM_FORMAT_INPUT_1_SUBSLOT_BYTES; +unsigned g_numUsbChan_In = NUM_USB_CHAN_IN_FS; /* Number of channels to/from the USB bus - initialised to FS for UAC1.0 */ +unsigned g_numUsbChan_Out = NUM_USB_CHAN_OUT_FS; +unsigned g_curSubSlot_Out = FS_STREAM_FORMAT_OUTPUT_1_SUBSLOT_BYTES; +unsigned g_curSubSlot_In = FS_STREAM_FORMAT_INPUT_1_SUBSLOT_BYTES; int sampsToWrite = DEFAULT_FREQ/1000; /* FS assumed here. Expect to be junked during a overflow before stream start */ int totalSampsToWrite = DEFAULT_FREQ/1000; int g_maxPacketSize = MAX_DEVICE_AUD_PACKET_SIZE_IN_FS; /* IN packet size. Init to something sensible, but expect to be re-set before stream start */ @@ -457,7 +457,7 @@ __builtin_unreachable(); packState = 0; /* Write last packet length into FIFO */ - int datasize = totalSampsToWrite * g_curSubSlot_In * g_numUsbChan_In; + unsigned datasize = totalSampsToWrite * g_curSubSlot_In * g_numUsbChan_In; write_via_xc_ptr(g_aud_to_host_wrptr, datasize); @@ -507,11 +507,11 @@ __builtin_unreachable(); /* In pipe has filled its buffer - we need to overflow * Accept the packet, and throw away the oldest in the buffer */ - int sampFreq; + unsigned sampFreq; GET_SHARED_GLOBAL(sampFreq, g_freqChange_sampFreq); int min, mid, max; GetADCCounts(sampFreq, min, mid, max); - int max_pkt_size = ((max * g_curSubSlot_In * g_numUsbChan_In + 3) & ~0x3) + 4; + unsigned max_pkt_size = ((max * g_curSubSlot_In * g_numUsbChan_In + 3) & ~0x3) + 4; /* Keep throwing away packets until buffer contains two packets */ do @@ -519,7 +519,7 @@ __builtin_unreachable(); unsigned rdPtr; /* Read length of packet in buffer at read pointer */ - int datalength; + unsigned datalength; GET_SHARED_GLOBAL(rdPtr, g_aud_to_host_rdptr); asm volatile("ldw %0, %1[0]":"=r"(datalength):"r"(rdPtr)); From 6beb1f34ae5537304c130debf9cf49d9dec5b12a Mon Sep 17 00:00:00 2001 From: xross Date: Tue, 27 Sep 2022 17:59:13 +0100 Subject: [PATCH 2/7] Tidy up first pulse of clock during startup in TDM mode --- lib_xua/src/core/audiohub/audiohub_initport.xc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/lib_xua/src/core/audiohub/audiohub_initport.xc b/lib_xua/src/core/audiohub/audiohub_initport.xc index e0e15161..fc763b04 100644 --- a/lib_xua/src/core/audiohub/audiohub_initport.xc +++ b/lib_xua/src/core/audiohub/audiohub_initport.xc @@ -52,7 +52,10 @@ void InitPorts_master(unsigned divide, buffered _XUA_CLK_DIR port:32 p_lrclk, bu } #endif - p_lrclk @ tmp <: 0x7FFFFFFF; + if(XUA_PCM_FORMAT == XUA_PCM_FORMAT_TDM) + p_lrclk @ tmp <: 0x80000000; + else + p_lrclk @ tmp <: 0x7FFFFFFF; #if (I2S_CHANS_ADC != 0) for(int i = 0; i < I2S_WIRES_ADC; i++) @@ -72,9 +75,7 @@ void InitPorts_master(unsigned divide, buffered _XUA_CLK_DIR port:32 p_lrclk, bu } #endif } - #else - void InitPorts_slave(unsigned divide, buffered _XUA_CLK_DIR port:32 p_lrclk, buffered _XUA_CLK_DIR port:32 p_bclk, buffered out port:32 (&?p_i2s_dac)[I2S_WIRES_DAC], buffered in port:32 (&?p_i2s_adc)[I2S_WIRES_ADC]) { #if (I2S_CHANS_ADC != 0 || I2S_CHANS_DAC != 0) From fe39cd7c11e7c5e6bc0e0a6f4335c9e15987cc66 Mon Sep 17 00:00:00 2001 From: xross Date: Tue, 27 Sep 2022 18:02:37 +0100 Subject: [PATCH 3/7] - Set I2S clocks to 8mA drive on XS3 - Set sample-delay on ADC data lines in TDM mode - Stare some port config code between I2S slave and master modes --- lib_xua/src/core/audiohub/xua_audiohub.xc | 1 - lib_xua/src/core/ports/audioports.xc | 45 ++++++++++------------- 2 files changed, 20 insertions(+), 26 deletions(-) diff --git a/lib_xua/src/core/audiohub/xua_audiohub.xc b/lib_xua/src/core/audiohub/xua_audiohub.xc index 6e07b1a3..75a9124c 100755 --- a/lib_xua/src/core/audiohub/xua_audiohub.xc +++ b/lib_xua/src/core/audiohub/xua_audiohub.xc @@ -122,7 +122,6 @@ static inline unsigned DoSampleTransfer(chanend ?c_out, const int readBuffNo, co if(dsdMode == DSD_MODE_DOP) dsdMode = DSD_MODE_OFF; #endif -#pragma xta endpoint "received_command" return command; } else diff --git a/lib_xua/src/core/ports/audioports.xc b/lib_xua/src/core/ports/audioports.xc index cf282747..a4c59d67 100644 --- a/lib_xua/src/core/ports/audioports.xc +++ b/lib_xua/src/core/ports/audioports.xc @@ -35,11 +35,16 @@ void ConfigAudioPorts( #if (I2S_CHANS_DAC != 0) || (I2S_CHANS_ADC != 0) #if (CODEC_MASTER == 0) +#ifdef __XS3A__ + /* Increase drive strength of clock ports to 8mA */ + asm volatile ("setc res[%0], %1" :: "r" (p_bclk), "r" (0x200006)); + asm volatile ("setc res[%0], %1" :: "r" (p_lrclk), "r" (0x200006)); +#endif + /* Note this call to stop_clock() will pause forever if the port clocking the clock-block is not low. * deliver() should return with this being the case */ stop_clock(clk_audio_bclk); - if(!isnull(p_lrclk)) { clearbuf(p_lrclk); @@ -73,26 +78,13 @@ void ConfigAudioPorts( configure_out_port_no_ready(p_lrclk, clk_audio_bclk, 0); } -#if (I2S_CHANS_DAC != 0) - /* Clock I2S output data ports from clock block */ - for(int i = 0; i < numPortsDac; i++) - { - configure_out_port_no_ready(p_i2s_dac[i], clk_audio_bclk, 0); - } -#endif + if(XUA_PCM_FORMAT == XUA_PCM_FORMAT_TDM) + { + for(int i = 0; i < I2S_WIRES_ADC; i++) + set_port_sample_delay(p_i2s_adc[i]); + } -#if (I2S_CHANS_ADC != 0) - /* Clock I2S input data ports from clock block */ - for(int i = 0; i < numPortsAdc; i++) - { - configure_in_port_no_ready(p_i2s_adc[i], clk_audio_bclk); - } -#endif - - /* Start clock blocks ticking */ - start_clock(clk_audio_bclk); - -#else /* CODEC_MASTER */ +#elif (CODEC_MASTER) /* Stop bit and master clock blocks */ stop_clock(clk_audio_bclk); @@ -100,8 +92,9 @@ void ConfigAudioPorts( /* Clock bclk clock-block from bclk pin */ configure_clock_src(clk_audio_bclk, p_bclk); + configure_in_port_no_ready(p_lrclk, clk_audio_bclk); - /* Do some clocking shifting to get data in the valid window */ + /* Do some clocking shifting to get data in the valid window */ /* E.g. Only shift when running at 88.2+ kHz TDM slave */ int bClkDelay_fall = 0; if(curSamFreq * I2S_CHANS_PER_FRAME * 32 >= 20000000) @@ -112,6 +105,9 @@ void ConfigAudioPorts( set_clock_fall_delay(clk_audio_bclk, bClkDelay_fall); +#endif + + #if (I2S_CHANS_DAC != 0) /* Clock I2S output data ports from b-clock clock block */ for(int i = 0; i < I2S_WIRES_DAC; i++) @@ -128,10 +124,9 @@ void ConfigAudioPorts( } #endif - configure_in_port_no_ready(p_lrclk, clk_audio_bclk); - + /* Start clock blocks ticking */ start_clock(clk_audio_bclk); -#endif -#endif + +#endif //#if (I2S_CHANS_DAC != 0) || (I2S_CHANS_ADC != 0) } From e1d09749128a6862dfc225ff2a1ba85bfbf1004b Mon Sep 17 00:00:00 2001 From: xross Date: Wed, 28 Sep 2022 11:09:33 +0100 Subject: [PATCH 4/7] test_i2s_loopback: - Add tracing options - Add TDM testing at 96khz - Fix up defines --- tests/test_i2s_loopback.py | 12 +++++-- tests/test_i2s_loopback/Makefile | 55 ++++++++++++++++++++++++-------- 2 files changed, 52 insertions(+), 15 deletions(-) diff --git a/tests/test_i2s_loopback.py b/tests/test_i2s_loopback.py index 48693d61..c824a355 100644 --- a/tests/test_i2s_loopback.py +++ b/tests/test_i2s_loopback.py @@ -51,7 +51,12 @@ def do_test( ] result = Pyxsim.run_on_simulator( - binary, simthreads=[], tester=tester, simargs=simargs, capfd=capfd + binary, + tester=tester, + simargs=simargs, + capfd=capfd, + instTracing=options.enabletracing, + vcdTracing=options.enablevcdtracing, ) return result @@ -60,7 +65,7 @@ def do_test( @pytest.mark.parametrize("i2s_role", ["master", "slave"]) @pytest.mark.parametrize("pcm_format", ["i2s", "tdm"]) @pytest.mark.parametrize("channel_count", [2, 8, 16]) -@pytest.mark.parametrize("sample_rate", ["48khz", "192khz"]) +@pytest.mark.parametrize("sample_rate", ["48khz", "96khz", "192khz"]) def test_i2s_loopback( i2s_role, pcm_format, channel_count, sample_rate, test_file, options, capfd ): @@ -68,6 +73,9 @@ def test_i2s_loopback( if pcm_format == "i2s" and channel_count == 16: pytest.skip("Invalid parameter combination") + if pcm_format == "i2s" and sample_rate not in ["48khz", "192khz"]: + pytest.skip("Invalid parameter combination") + if pcm_format == "tdm" and channel_count == 2: pytest.skip("Invalid parameter combination") diff --git a/tests/test_i2s_loopback/Makefile b/tests/test_i2s_loopback/Makefile index 7fb0bb12..32615bb1 100644 --- a/tests/test_i2s_loopback/Makefile +++ b/tests/test_i2s_loopback/Makefile @@ -1,74 +1,99 @@ TARGET = xk-audio-216-mc.xn USED_MODULES = lib_xua lib_i2c lib_logging -BUILD_FLAGS = -O0 -g -lflash -DXUD_SERIES_SUPPORT=4 -DXUD_CORE_CLOCK=600 -fxscope -save-temps -march=xs2a -DUSB_TILE=tile[1] +BUILD_FLAGS = -O0 -g -lflash -DXUD_CORE_CLOCK=600 -fxscope -save-temps -march=xs2a -DUSB_TILE=tile[1] BUILD_FLAGS_i2s_master_2in_2out_48khz = $(BUILD_FLAGS) \ - -D ADAT_RX=0 -D ADAT_TX=0 -D SPDIF_RX=0 -D SPDIF_TX=0 -D MIDI=0 \ + -D XUA_ADAT_RX_EN=0 -D XUA_ADAT_TX_EN=0 -D XUA_SPDIF_RX_EN=0 -D XUA_SPDIF_TX_EN=0 -D MIDI=0 \ -D NUM_USB_CHAN_IN=2 -D NUM_USB_CHAN_OUT=2 -DI2S_CHANS_ADC=2 -DI2S_CHANS_DAC=2 \ -D DEFAULT_FREQ=48000 BUILD_FLAGS_i2s_slave_2in_2out_48khz = $(BUILD_FLAGS) \ - -D ADAT_RX=0 -D ADAT_TX=0 -D SPDIF_RX=0 -D SPDIF_TX=0 -D MIDI=0 \ + -D XUA_ADAT_RX_EN=0 -D XUA_ADAT_TX_EN=0 -D XUA_SPDIF_RX_EN=0 -D XUA_SPDIF_TX_EN=0 -D MIDI=0 \ -D NUM_USB_CHAN_IN=2 -D NUM_USB_CHAN_OUT=2 -DI2S_CHANS_ADC=2 -DI2S_CHANS_DAC=2 \ -D DEFAULT_FREQ=48000 -DCODEC_MASTER=1 BUILD_FLAGS_i2s_master_2in_2out_192khz = $(BUILD_FLAGS) \ - -D ADAT_RX=0 -D ADAT_TX=0 -D SPDIF_RX=0 -D SPDIF_TX=0 -D MIDI=0 \ + -D XUA_ADAT_RX_EN=0 -D XUA_ADAT_TX_EN=0 -D XUA_SPDIF_RX_EN=0 -D XUA_SPDIF_TX_EN=0 -D MIDI=0 \ -D NUM_USB_CHAN_IN=2 -D NUM_USB_CHAN_OUT=2 -D I2S_CHANS_ADC=2 -D I2S_CHANS_DAC=2 \ -D DEFAULT_FREQ=192000 BUILD_FLAGS_i2s_slave_2in_2out_192khz = $(BUILD_FLAGS) \ - -D ADAT_RX=0 -D ADAT_TX=0 -D SPDIF_RX=0 -D SPDIF_TX=0 -D MIDI=0 \ + -D XUA_ADAT_RX_EN=0 -D XUA_ADAT_TX_EN=0 -D XUA_SPDIF_RX_EN=0 -D XUA_SPDIF_TX_EN=0 -D MIDI=0 \ -D NUM_USB_CHAN_IN=2 -D NUM_USB_CHAN_OUT=2 -DI2S_CHANS_ADC=2 -DI2S_CHANS_DAC=2 \ -D DEFAULT_FREQ=192000 -DCODEC_MASTER=1 BUILD_FLAGS_i2s_master_8in_8out_48khz = $(BUILD_FLAGS) \ - -D ADAT_RX=0 -D ADAT_TX=0 -D SPDIF_RX=0 -D SPDIF_TX=0 -D MIDI=0 \ + -D XUA_ADAT_RX_EN=0 -D XUA_ADAT_TX_EN=0 -D XUA_SPDIF_RX_EN=0 -D XUA_SPDIF_TX_EN=0 -D MIDI=0 \ -D NUM_USB_CHAN_IN=8 -D NUM_USB_CHAN_OUT=8 -D I2S_CHANS_ADC=8 -D I2S_CHANS_DAC=8 \ -D DEFAULT_FREQ=48000 BUILD_FLAGS_i2s_slave_8in_8out_48khz = $(BUILD_FLAGS) \ - -D ADAT_RX=0 -D ADAT_TX=0 -D SPDIF_RX=0 -D SPDIF_TX=0 -D MIDI=0 \ + -D XUA_ADAT_RX_EN=0 -D XUA_ADAT_TX_EN=0 -D XUA_SPDIF_RX_EN=0 -D XUA_SPDIF_TX_EN=0 -D MIDI=0 \ -D NUM_USB_CHAN_IN=8 -D NUM_USB_CHAN_OUT=8 -D I2S_CHANS_ADC=8 -D I2S_CHANS_DAC=8 \ -D DEFAULT_FREQ=48000 -DCODEC_MASTER=1 BUILD_FLAGS_i2s_master_8in_8out_192khz = $(BUILD_FLAGS) \ - -D ADAT_RX=0 -D ADAT_TX=0 -D SPDIF_RX=0 -D SPDIF_TX=0 -D MIDI=0 \ + -D XUA_ADAT_RX_EN=0 -D XUA_ADAT_TX_EN=0 -D XUA_SPDIF_RX_EN=0 -D XUA_SPDIF_TX_EN=0 -D MIDI=0 \ -D NUM_USB_CHAN_IN=8 -D NUM_USB_CHAN_OUT=8 -D I2S_CHANS_ADC=8 -D I2S_CHANS_DAC=8 \ -D DEFAULT_FREQ=192000 \ -O2 # optimisations to meet timing BUILD_FLAGS_i2s_slave_8in_8out_192khz = $(BUILD_FLAGS) \ - -D ADAT_RX=0 -D ADAT_TX=0 -D SPDIF_RX=0 -D SPDIF_TX=0 -D MIDI=0 \ + -D XUA_ADAT_RX_EN=0 -D XUA_ADAT_TX_EN=0 -D XUA_SPDIF_RX_EN=0 -D XUA_SPDIF_TX_EN=0 -D MIDI=0 \ -D NUM_USB_CHAN_IN=8 -D NUM_USB_CHAN_OUT=8 -D I2S_CHANS_ADC=8 -D I2S_CHANS_DAC=8 \ -D DEFAULT_FREQ=192000 -DCODEC_MASTER=1 \ -O2 # optimisations to meet timing BUILD_FLAGS_tdm_master_8in_8out_48khz = $(BUILD_FLAGS) -D XUA_PCM_FORMAT=XUA_PCM_FORMAT_TDM \ - -D ADAT_RX=0 -D ADAT_TX=0 -D SPDIF_RX=0 -D SPDIF_TX=0 -D MIDI=0 \ + -D XUA_ADAT_RX_EN=0 -D XUA_ADAT_TX_EN=0 -D XUA_SPDIF_RX_EN=0 -D XUA_SPDIF_TX_EN=0 -D MIDI=0 \ -D NUM_USB_CHAN_IN=8 -D NUM_USB_CHAN_OUT=8 -D I2S_CHANS_ADC=8 -D I2S_CHANS_DAC=8 \ -D DEFAULT_FREQ=48000 \ -O2 # optimisations to meet timing +BUILD_FLAGS_tdm_master_8in_8out_96khz = $(BUILD_FLAGS) -D XUA_PCM_FORMAT=XUA_PCM_FORMAT_TDM \ + -D XUA_ADAT_RX_EN=0 -D XUA_ADAT_TX_EN=0 -D XUA_SPDIF_RX_EN=0 -D XUA_SPDIF_TX_EN=0 -D MIDI=0 \ + -D NUM_USB_CHAN_IN=8 -D NUM_USB_CHAN_OUT=8 -D I2S_CHANS_ADC=8 -D I2S_CHANS_DAC=8 \ + -D DEFAULT_FREQ=96000 \ + -O3 # optimisations to meet timing + BUILD_FLAGS_tdm_slave_8in_8out_48khz = $(BUILD_FLAGS) -D XUA_PCM_FORMAT=XUA_PCM_FORMAT_TDM \ - -D ADAT_RX=0 -D ADAT_TX=0 -D SPDIF_RX=0 -D SPDIF_TX=0 -D MIDI=0 \ + -D XUA_ADAT_RX_EN=0 -D XUA_ADAT_TX_EN=0 -D XUA_SPDIF_RX_EN=0 -D XUA_SPDIF_TX_EN=0 -D MIDI=0 \ -D NUM_USB_CHAN_IN=8 -D NUM_USB_CHAN_OUT=8 -D I2S_CHANS_ADC=8 -D I2S_CHANS_DAC=8 \ -D DEFAULT_FREQ=48000 -DCODEC_MASTER=1 \ -O2 # optimisations to meet timing +BUILD_FLAGS_tdm_slave_8in_8out_96khz = $(BUILD_FLAGS) -D XUA_PCM_FORMAT=XUA_PCM_FORMAT_TDM \ + -D XUA_ADAT_RX_EN=0 -D XUA_ADAT_TX_EN=0 -D XUA_SPDIF_RX_EN=0 -D XUA_SPDIF_TX_EN=0 -D MIDI=0 \ + -D NUM_USB_CHAN_IN=8 -D NUM_USB_CHAN_OUT=8 -D I2S_CHANS_ADC=8 -D I2S_CHANS_DAC=8 \ + -D DEFAULT_FREQ=96000 -DCODEC_MASTER=1 \ + -O2 # optimisations to meet timing + BUILD_FLAGS_tdm_master_16in_16out_48khz = $(BUILD_FLAGS) -D XUA_PCM_FORMAT=XUA_PCM_FORMAT_TDM \ - -D ADAT_RX=0 -D ADAT_TX=0 -D SPDIF_RX=0 -D SPDIF_TX=0 -D MIDI=0 \ + -D XUA_ADAT_RX_EN=0 -D XUA_ADAT_TX_EN=0 -D XUA_SPDIF_RX_EN=0 -D XUA_SPDIF_TX_EN=0 -D MIDI=0 \ -D NUM_USB_CHAN_IN=16 -D NUM_USB_CHAN_OUT=16 -D I2S_CHANS_ADC=16 -D I2S_CHANS_DAC=16 \ -D DEFAULT_FREQ=48000 \ -O2 # optimisations to meet timing +BUILD_FLAGS_tdm_master_16in_16out_96khz = $(BUILD_FLAGS) -D XUA_PCM_FORMAT=XUA_PCM_FORMAT_TDM \ + -D XUA_ADAT_RX_EN=0 -D XUA_ADAT_TX_EN=0 -D XUA_SPDIF_RX_EN=0 -D XUA_SPDIF_TX_EN=0 -D MIDI=0 \ + -D NUM_USB_CHAN_IN=16 -D NUM_USB_CHAN_OUT=16 -D I2S_CHANS_ADC=16 -D I2S_CHANS_DAC=16 \ + -D DEFAULT_FREQ=96000 \ + -O2 # optimisations to meet timing + BUILD_FLAGS_tdm_slave_16in_16out_48khz = $(BUILD_FLAGS) -D XUA_PCM_FORMAT=XUA_PCM_FORMAT_TDM \ - -D ADAT_RX=0 -D ADAT_TX=0 -D SPDIF_RX=0 -D SPDIF_TX=0 -D MIDI=0 \ + -D XUA_ADAT_RX_EN=0 -D XUA_ADAT_TX_EN=0 -D XUA_SPDIF_RX_EN=0 -D XUA_SPDIF_TX_EN=0 -D MIDI=0 \ -D NUM_USB_CHAN_IN=16 -D NUM_USB_CHAN_OUT=16 -D I2S_CHANS_ADC=16 -D I2S_CHANS_DAC=16 \ -D DEFAULT_FREQ=48000 -DCODEC_MASTER=1 \ -O2 # optimisations to meet timing +BUILD_FLAGS_tdm_slave_16in_16out_96khz = $(BUILD_FLAGS) -D XUA_PCM_FORMAT=XUA_PCM_FORMAT_TDM \ + -D XUA_ADAT_RX_EN=0 -D XUA_ADAT_TX_EN=0 -D XUA_SPDIF_RX_EN=0 -D XUA_SPDIF_TX_EN=0 -D MIDI=0 \ + -D NUM_USB_CHAN_IN=16 -D NUM_USB_CHAN_OUT=16 -D I2S_CHANS_ADC=16 -D I2S_CHANS_DAC=16 \ + -D DEFAULT_FREQ=96000 -DCODEC_MASTER=1 \ + -O2 # optimisations to meet timing + + #XCC_FLAGS_hardware_i2s_master_2in_2out_48khz = -D HARDWARE $(BUILD_FLAGS_i2s_master_2in_2out_48khz) #XCC_FLAGS_hardware_i2s_master_2in_2out_192khz = -D HARDWARE $(BUILD_FLAGS_i2s_master_2in_2out_192khz) #XCC_FLAGS_hardware_i2s_master_8in_8out_48khz = -D HARDWARE $(BUILD_FLAGS_i2s_master_8in_8out_48khz) @@ -88,10 +113,14 @@ XCC_FLAGS_simulation_i2s_master_8in_8out_192khz = -D SIMULATION $(BUILD_FLAGS_i2 XCC_FLAGS_simulation_i2s_slave_8in_8out_192khz = -D SIMULATION $(BUILD_FLAGS_i2s_slave_8in_8out_192khz) XCC_FLAGS_simulation_tdm_master_8in_8out_48khz = -D SIMULATION $(BUILD_FLAGS_tdm_master_8in_8out_48khz) +XCC_FLAGS_simulation_tdm_master_8in_8out_96khz = -D SIMULATION $(BUILD_FLAGS_tdm_master_8in_8out_96khz) XCC_FLAGS_simulation_tdm_slave_8in_8out_48khz = -D SIMULATION $(BUILD_FLAGS_tdm_slave_8in_8out_48khz) +XCC_FLAGS_simulation_tdm_slave_8in_8out_96khz = -D SIMULATION $(BUILD_FLAGS_tdm_slave_8in_8out_96khz) XCC_FLAGS_simulation_tdm_master_16in_16out_48khz = -D SIMULATION $(BUILD_FLAGS_tdm_master_16in_16out_48khz) +XCC_FLAGS_simulation_tdm_master_16in_16out_96khz = -D SIMULATION $(BUILD_FLAGS_tdm_master_16in_16out_96khz) XCC_FLAGS_simulation_tdm_slave_16in_16out_48khz = -D SIMULATION $(BUILD_FLAGS_tdm_slave_16in_16out_48khz) +XCC_FLAGS_simulation_tdm_slave_16in_16out_96khz = -D SIMULATION $(BUILD_FLAGS_tdm_slave_16in_16out_96khz) XMOS_MAKE_PATH ?= ../.. -include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common From b7a90a3235f036712fc0c513344d0e59d5ca2101 Mon Sep 17 00:00:00 2001 From: xross Date: Wed, 28 Sep 2022 11:27:12 +0100 Subject: [PATCH 5/7] Changelog update --- CHANGELOG.rst | 3 +++ lib_xua/src/core/audiohub/audiohub_initport.xc | 6 +++--- lib_xua/src/core/ports/audioports.xc | 12 +++++++----- 3 files changed, 13 insertions(+), 8 deletions(-) diff --git a/CHANGELOG.rst b/CHANGELOG.rst index ffce0be7..12719bb9 100644 --- a/CHANGELOG.rst +++ b/CHANGELOG.rst @@ -7,6 +7,9 @@ UNRELEASED * CHANGED: Define ADAT_RX renamed to XUA_ADAT_RX_EN * CHANGED: Define ADAT_TX renamed to XUA_ADAT_TX_EN * CHANGED: Define SPDIF_RX renamed to XUA_SPDIF_RX_EN + * CHANGED: Drive strength of I2S clock lines upped to 8mA on xCORE.ai + * CHANGED: ADC datalines sampled on falling edge of clock in TDM mode + * CHANGED: Improved startup behaviour of TDM clocks * FIXED: Intermittent underflow at MAX_FREQ on input stream start due to insufficient packet buffering diff --git a/lib_xua/src/core/audiohub/audiohub_initport.xc b/lib_xua/src/core/audiohub/audiohub_initport.xc index fc763b04..82fc3346 100644 --- a/lib_xua/src/core/audiohub/audiohub_initport.xc +++ b/lib_xua/src/core/audiohub/audiohub_initport.xc @@ -52,10 +52,10 @@ void InitPorts_master(unsigned divide, buffered _XUA_CLK_DIR port:32 p_lrclk, bu } #endif - if(XUA_PCM_FORMAT == XUA_PCM_FORMAT_TDM) - p_lrclk @ tmp <: 0x80000000; + if(XUA_PCM_FORMAT == XUA_PCM_FORMAT_TDM) + p_lrclk @ tmp <: 0x80000000; else - p_lrclk @ tmp <: 0x7FFFFFFF; + p_lrclk @ tmp <: 0x7FFFFFFF; #if (I2S_CHANS_ADC != 0) for(int i = 0; i < I2S_WIRES_ADC; i++) diff --git a/lib_xua/src/core/ports/audioports.xc b/lib_xua/src/core/ports/audioports.xc index a4c59d67..cc9ce57b 100644 --- a/lib_xua/src/core/ports/audioports.xc +++ b/lib_xua/src/core/ports/audioports.xc @@ -78,11 +78,13 @@ void ConfigAudioPorts( configure_out_port_no_ready(p_lrclk, clk_audio_bclk, 0); } - if(XUA_PCM_FORMAT == XUA_PCM_FORMAT_TDM) - { - for(int i = 0; i < I2S_WIRES_ADC; i++) - set_port_sample_delay(p_i2s_adc[i]); - } + if(XUA_PCM_FORMAT == XUA_PCM_FORMAT_TDM) + { + for(int i = 0; i < I2S_WIRES_ADC; i++) + { + set_port_sample_delay(p_i2s_adc[i]); + } + } #elif (CODEC_MASTER) From 1259fb68fdd8cacfb06ef45468f4dbcd39794ff0 Mon Sep 17 00:00:00 2001 From: xross Date: Wed, 28 Sep 2022 18:59:18 +0100 Subject: [PATCH 6/7] Fix build issue with no I2S input --- lib_xua/src/core/ports/audioports.xc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lib_xua/src/core/ports/audioports.xc b/lib_xua/src/core/ports/audioports.xc index cc9ce57b..d6e85d3a 100644 --- a/lib_xua/src/core/ports/audioports.xc +++ b/lib_xua/src/core/ports/audioports.xc @@ -78,6 +78,7 @@ void ConfigAudioPorts( configure_out_port_no_ready(p_lrclk, clk_audio_bclk, 0); } +#if (I2S_CHANS_ADC != 0) if(XUA_PCM_FORMAT == XUA_PCM_FORMAT_TDM) { for(int i = 0; i < I2S_WIRES_ADC; i++) @@ -85,6 +86,7 @@ void ConfigAudioPorts( set_port_sample_delay(p_i2s_adc[i]); } } +#endif #elif (CODEC_MASTER) From d754bff62b0dcfdb3c61e16571655e6c058f5a6f Mon Sep 17 00:00:00 2001 From: xross Date: Wed, 28 Sep 2022 19:04:33 +0100 Subject: [PATCH 7/7] Manually fix decouple merge --- lib_xua/src/core/buffer/decouple/decouple.xc | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/lib_xua/src/core/buffer/decouple/decouple.xc b/lib_xua/src/core/buffer/decouple/decouple.xc index 668af697..2e64ecd0 100644 --- a/lib_xua/src/core/buffer/decouple/decouple.xc +++ b/lib_xua/src/core/buffer/decouple/decouple.xc @@ -68,18 +68,18 @@ static xc_ptr p_multIn; #endif #if (AUDIO_CLASS == 2) -unsigned g_numUsbChan_In = NUM_USB_CHAN_IN; /* Number of channels to/from the USB bus - initialised to HS for UAC2.0 */ -unsigned g_numUsbChan_Out = NUM_USB_CHAN_OUT; -unsigned g_curSubSlot_Out = HS_STREAM_FORMAT_OUTPUT_1_SUBSLOT_BYTES; -unsigned g_curSubSlot_In = HS_STREAM_FORMAT_INPUT_1_SUBSLOT_BYTES; +int g_numUsbChan_In = NUM_USB_CHAN_IN; /* Number of channels to/from the USB bus - initialised to HS for UAC2.0 */ +int g_numUsbChan_Out = NUM_USB_CHAN_OUT; +int g_curSubSlot_Out = HS_STREAM_FORMAT_OUTPUT_1_SUBSLOT_BYTES; +int g_curSubSlot_In = HS_STREAM_FORMAT_INPUT_1_SUBSLOT_BYTES; int sampsToWrite = DEFAULT_FREQ/8000; /* HS assumed here. Expect to be junked during a overflow before stream start */ int totalSampsToWrite = DEFAULT_FREQ/8000; int g_maxPacketSize = MAX_DEVICE_AUD_PACKET_SIZE_IN_HS; /* IN packet size. Init to something sensible, but expect to be re-set before stream start */ #else -unsigned g_numUsbChan_In = NUM_USB_CHAN_IN_FS; /* Number of channels to/from the USB bus - initialised to FS for UAC1.0 */ -unsigned g_numUsbChan_Out = NUM_USB_CHAN_OUT_FS; -unsigned g_curSubSlot_Out = FS_STREAM_FORMAT_OUTPUT_1_SUBSLOT_BYTES; -unsigned g_curSubSlot_In = FS_STREAM_FORMAT_INPUT_1_SUBSLOT_BYTES; +int g_numUsbChan_In = NUM_USB_CHAN_IN_FS; /* Number of channels to/from the USB bus - initialised to FS for UAC1.0 */ +int g_numUsbChan_Out = NUM_USB_CHAN_OUT_FS; +int g_curSubSlot_Out = FS_STREAM_FORMAT_OUTPUT_1_SUBSLOT_BYTES; +int g_curSubSlot_In = FS_STREAM_FORMAT_INPUT_1_SUBSLOT_BYTES; int sampsToWrite = DEFAULT_FREQ/1000; /* FS assumed here. Expect to be junked during a overflow before stream start */ int totalSampsToWrite = DEFAULT_FREQ/1000; int g_maxPacketSize = MAX_DEVICE_AUD_PACKET_SIZE_IN_FS; /* IN packet size. Init to something sensible, but expect to be re-set before stream start */ @@ -459,7 +459,7 @@ __builtin_unreachable(); packState = 0; /* Write last packet length into FIFO */ - unsigned datasize = totalSampsToWrite * g_curSubSlot_In * g_numUsbChan_In; + int datasize = totalSampsToWrite * g_curSubSlot_In * g_numUsbChan_In; GET_SHARED_GLOBAL(wrPtr, g_aud_to_host_wrptr); write_via_xc_ptr(wrPtr, datasize); @@ -515,7 +515,6 @@ __builtin_unreachable(); GET_SHARED_GLOBAL(sampFreq, g_freqChange_sampFreq); int min, mid, max; GetADCCounts(sampFreq, min, mid, max); - const int max_pkt_size = ((max * g_curSubSlot_In * g_numUsbChan_In + 3) & ~0x3) + 4; int rdPtr; GET_SHARED_GLOBAL(rdPtr, g_aud_to_host_rdptr);