Update docs for sync mode with sw_pll
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@@ -39,8 +39,11 @@ Setting the synchronisation mode of the device is done using the define in :ref:
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- USB synchronisation mode
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- USB synchronisation mode
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- ``XUA_SYNCMODE_ASYNC``
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- ``XUA_SYNCMODE_ASYNC``
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When operating in synchronous mode an external Cirrus Logic CS2100 device is required for master clock
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When operating in synchronous mode a local master clock must be generated that is synchronised to the incoming
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generation. The codebase expects to drive a synchronisation signal to this external device
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SoF rate from USB. Either an external Cirrus Logic CS2100 device is required for this purpose
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or, on xcore.ai devices, the on-chip application PLL may be used via lib_sw_pll.
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In the case of using the CS2100, the codebase expects to drive a synchronisation signal to this external device
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as a reference.
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The programmer should ensure the define in :ref:`opt_sync_ref_defines` is set appropriately.
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The programmer should ensure the define in :ref:`opt_sync_ref_defines` is set appropriately.
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@@ -56,8 +59,11 @@ The programmer should ensure the define in :ref:`opt_sync_ref_defines` is set ap
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* - ``PLL_REF_TILE``
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* - ``PLL_REF_TILE``
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- Tile location of reference to CS2100 device
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- Tile location of reference to CS2100 device
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- ``AUDIO_IO_TILE``
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- ``AUDIO_IO_TILE``
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* - ``XUA_USE_SW_PLL``
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- Whether or not to use sw_pll to recover the clock (xcore.ai only)
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- 1 for xcore.ai targets. May be overridden to 0 in ``xua_conf.h``
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The codebase expects this reference signal port to be defined in the application XN file as ``PORT_PLL_REF``.
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The codebase expects the CS2100 reference signal port to be defined in the application XN file as ``PORT_PLL_REF``.
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This may be a port of any bit-width, however, connection to bit[0] is assumed::
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This may be a port of any bit-width, however, connection to bit[0] is assumed::
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<Port Location="XS1_PORT_1A" Name="PORT_PLL_REF"/>
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<Port Location="XS1_PORT_1A" Name="PORT_PLL_REF"/>
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