Vergil_Wong/lib_xua
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Remove TDM ADC clocking on neg edge

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This commit is contained in:
xross
2022-11-01 19:24:25 +00:00
parent 28be17282f
commit a1946f340a
2 changed files with 2 additions and 5 deletions
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1
lib_xua/src/core/audiohub/audiohub_initport.xc
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@@ -38,7 +38,6 @@ void InitPorts_master(unsigned divide, buffered _XUA_CLK_DIR port:32 p_lrclk, bu
} }
#endif #endif
#pragma xta endpoint "divide_1"
unsigned tmp; unsigned tmp;
p_lrclk <: 0 @ tmp; p_lrclk <: 0 @ tmp;
tmp += 100; tmp += 100;

6
lib_xua/src/core/ports/audioports.xc
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@@ -84,8 +84,8 @@ void ConfigAudioPorts(
{ {
for(int i = 0; i < I2S_WIRES_ADC; i++) for(int i = 0; i < I2S_WIRES_ADC; i++)
{ {
set_port_sample_delay(p_i2s_adc[i]); //set_port_sample_delay(p_i2s_adc[i]);
set_pad_delay(p_i2s_adc[i], 4); //set_pad_delay(p_i2s_adc[i], 4);
} }
} }
#endif #endif
@@ -110,10 +110,8 @@ void ConfigAudioPorts(
} }
set_clock_fall_delay(clk_audio_bclk, bClkDelay_fall); set_clock_fall_delay(clk_audio_bclk, bClkDelay_fall);
#endif #endif
#if (I2S_CHANS_DAC != 0) #if (I2S_CHANS_DAC != 0)
/* Clock I2S output data ports from b-clock clock block */ /* Clock I2S output data ports from b-clock clock block */
for(int i = 0; i < I2S_WIRES_DAC; i++) for(int i = 0; i < I2S_WIRES_DAC; i++)