Vergil_Wong/lib_xua
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Ed
2024-01-15 10:39:09 +00:00
parent 57debd0558
commit a4e6fd0194
3 changed files with 7 additions and 6 deletions
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7
lib_xua/src/core/clocking/clockgen.xc
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@@ -107,7 +107,6 @@ static inline void setClockValidity(chanend c_interruptControl, int clkIndex, in
{ {
clockValid[clkIndex] = valid; clockValid[clkIndex] = valid;
outInterrupt(c_interruptControl, clockId[clkIndex]); outInterrupt(c_interruptControl, clockId[clkIndex]);
printstr("clockValid=");printintln(valid);
#ifdef CLOCK_VALIDITY_CALL #ifdef CLOCK_VALIDITY_CALL
#if (XUA_ADAT_RX_EN) #if (XUA_ADAT_RX_EN)
@@ -349,6 +348,7 @@ void clockGen ( streaming chanend ?c_spdif_rx,
int reset_sw_pll_pfd = 1; int reset_sw_pll_pfd = 1;
int require_ack_to_audio = 0; int require_ack_to_audio = 0;
/* Set selected_mclk_rate_ptr to point at local var selected_mclk_rate */
unsafe { unsafe {
selected_mclk_rate_ptr = &selected_mclk_rate; selected_mclk_rate_ptr = &selected_mclk_rate;
} }
@@ -535,7 +535,8 @@ void clockGen ( streaming chanend ?c_spdif_rx,
#if ((XUA_SPDIF_RX_EN || XUA_ADAT_RX_EN) && USE_SW_PLL) #if ((XUA_SPDIF_RX_EN || XUA_ADAT_RX_EN) && USE_SW_PLL)
case inuint_byref(c_sigma_delta, tmp): case inuint_byref(c_sigma_delta, tmp):
/* Send ACK back to audiohub to allow I2S to start */ /* Send ACK back to audiohub to allow I2S to start
This happens only on SDM restart and only once */
if(require_ack_to_audio) if(require_ack_to_audio)
{ {
c_mclk_change <: tmp; c_mclk_change <: tmp;
@@ -545,7 +546,7 @@ void clockGen ( streaming chanend ?c_spdif_rx,
#endif #endif
#if (XUA_SPDIF_RX_EN || XUA_ADAT_RX_EN) #if (XUA_SPDIF_RX_EN || XUA_ADAT_RX_EN)
/* Receive notification of audio streaming settings change */ /* Receive notification of audio streaming settings change and store */
case c_mclk_change :> selected_mclk_rate: case c_mclk_change :> selected_mclk_rate:
c_mclk_change :> selected_sample_rate; c_mclk_change :> selected_sample_rate;
#if USE_SW_PLL #if USE_SW_PLL

2
lib_xua/src/core/clocking/sw_pll_wrapper.h
View File

@@ -58,7 +58,7 @@ void do_sw_pll_phase_frequency_detector_dig_rx( unsigned short mclk_time_stamp,
* \param sw_pll Reference to a software pll state struct to be initialised. * \param sw_pll Reference to a software pll state struct to be initialised.
* \param mClk The current nominal mClk frequency. * \param mClk The current nominal mClk frequency.
* *
* returns The SDM update interval and the initial DCO setting for nominal frequency */ * returns The SDM update interval in ticks and the initial DCO setting for nominal frequency */
{unsigned, unsigned} InitSWPLL(sw_pll_state_t &sw_pll, unsigned mClk); {unsigned, unsigned} InitSWPLL(sw_pll_state_t &sw_pll, unsigned mClk);
#endif /* USE_SW_PLL */ #endif /* USE_SW_PLL */

4
lib_xua/src/core/clocking/sw_pll_wrapper.xc
View File

@@ -126,7 +126,7 @@ void SigmaDeltaTask(chanend c_sigma_delta, unsigned * unsafe selected_mclk_rate_
unsafe unsafe
{ {
printf("SigmaDeltaTask: %u\n", *selected_mclk_rate_ptr); /* initialse the SDM and gather SDM initial settings */
{sdm_interval, dco_setting} = InitSWPLL(sw_pll, (unsigned)*selected_mclk_rate_ptr); {sdm_interval, dco_setting} = InitSWPLL(sw_pll, (unsigned)*selected_mclk_rate_ptr);
} }
@@ -162,7 +162,7 @@ void SigmaDeltaTask(chanend c_sigma_delta, unsigned * unsafe selected_mclk_rate_
} }
break; break;
// Do nothing & fall-through /* Do nothing & fall-through. Above case polls only once per loop */
default: default:
break; break;
} }