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Added initial AN00247

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xross
2018-03-29 13:32:54 +01:00
parent f1aca129f2
commit b4090602ad
15 changed files with 1085 additions and 3 deletions
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103
examples/AN00247_xua_example_spdif_tx/src/app_xua_simple.xc Normal file
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// Copyright (c) 2017-2018, XMOS Ltd, All rights reserved
/* A very simple *example* of a USB audio application (and as such is un-verified for production)
*
* It uses the main blocks from the lib_xua
*
* - S/PDIF output only
* - No DFU
*
*/
#include <xs1.h>
#include <platform.h>
#include "xua.h"
#include "xud_device.h"
/* From lib_spdif */
#include "spdif.h"
/* Lib_spdif port declarations. Note, the defines come from the xn file */
buffered out port:32 p_spdif_tx2 = PORT_SPDIF_OUT; /* SPDIF transmit port */
/* Lib_xua port declarations. Note, the defines come from the xn file */
in port p_mclk_in = PORT_MCLK_IN; /* Master clock for the audio IO tile */
/* Resources for USB feedback */
in port p_for_mclk_count = PORT_MCLK_COUNT; /* Extra port for counting master clock ticks */
in port p_mclk_in_usb = PORT_MCLK_IN_USB; /* Extra master clock input for the USB tile */
/* Clock-block declarations */
clock clk_audio_mclk = on tile[0]: XS1_CLKBLK_5; /* Master clock */
clock clk_audio_mclk_usb = on tile[1]: XS1_CLKBLK_1; /* Master clock for USB tile */
/* Endpoint type tables - informs XUD what the transfer types for each Endpoint in use and also
* if the endpoint wishes to be informed of USB bus resets */
XUD_EpType epTypeTableOut[] = {XUD_EPTYPE_CTL | XUD_STATUS_ENABLE, XUD_EPTYPE_ISO};
XUD_EpType epTypeTableIn[] = {XUD_EPTYPE_CTL | XUD_STATUS_ENABLE, XUD_EPTYPE_ISO};
int main()
{
/* Channels for lib_xud */
chan c_ep_out[2];
chan c_ep_in[2];
/* Channel for communicating SOF notifications from XUD to the Buffering cores */
chan c_sof;
/* Channel for audio data between buffering cores and AudioHub/IO core */
chan c_aud;
/* Channel for communicating control messages from EP0 to the rest of the device (via the buffering cores) */
chan c_aud_ctl;
/* Channel for communication between AudioHub and S/PDIF transmitter */
chan c_spdif_tx;
par
{
/* Low level USB device layer core */
on tile[1]: XUD_Main(c_ep_out, 2, c_ep_in, 2, c_sof, epTypeTableOut, epTypeTableIn, null, null, -1, XUD_SPEED_HS, XUD_PWR_SELF);
/* Endpoint 0 core from lib_xua */
/* Note, since we are not using many features we pass in null for quite a few params.. */
on tile[1]: XUA_Endpoint0(c_ep_out[0], c_ep_in[0], c_aud_ctl, null, null, null, null);
/* Buffering cores - handles audio data to/from EP's and gives/gets data to/from the audio I/O core */
/* Note, this spawns two cores */
on tile[1]: {
/* Connect master-clock clock-block to clock-block pin */
set_clock_src(clk_audio_mclk_usb, p_mclk_in_usb); /* Clock clock-block from mclk pin */
set_port_clock(p_for_mclk_count, clk_audio_mclk_usb); /* Clock the "count" port from the clock block */
start_clock(clk_audio_mclk_usb); /* Set the clock off running */
XUA_Buffer(c_ep_out[1], c_ep_in[1], c_sof, c_aud_ctl, p_for_mclk_count, c_aud);
}
/* AudioHub() (I2S) and S/SPDIF Tx are on the same tile */
on tile[0]: {
/* Setup S/PDIF tx port from clock etc - note we do this before par to avoid parallel usage */
spdif_tx_port_config(p_spdif_tx2, clk_audio_mclk, p_mclk_in, 7);
par
{
while(1)
{
/* Run the S/PDIF transmitter task */
spdif_tx(p_spdif_tx2, c_spdif_tx);
}
/* AudioHub/IO core does most of the audio IO i.e. I2S (also serves as a hub for all audio) */
/* Note, since we are not using I2S we pass in null for LR and Bit clock ports and the I2S dataline ports */
XUA_AudioHub(c_aud, clk_audio_mclk, null, p_mclk_in, null, null, null, null, c_spdif_tx);
}
}
}
return 0;
}

32
examples/AN00247_xua_example_spdif_tx/src/cs4384.h Normal file
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// Copyright (c) 2017-2018, XMOS Ltd, All rights reserved
#ifndef CS4384_H_
#define CS4384_H_
//Address on I2C bus
#define CS4384_I2C_ADDR (0x18)
//Register Addresess
#define CS4384_CHIP_REV 0x01
#define CS4384_MODE_CTRL 0x02
#define CS4384_PCM_CTRL 0x03
#define CS4384_DSD_CTRL 0x04
#define CS4384_FLT_CTRL 0x05
#define CS4384_INV_CTRL 0x06
#define CS4384_GRP_CTRL 0x07
#define CS4384_RMP_MUTE 0x08
#define CS4384_MUTE_CTRL 0x09
#define CS4384_MIX_PR1 0x0a
#define CS4384_VOL_A1 0x0b
#define CS4384_VOL_B1 0x0c
#define CS4384_MIX_PR2 0x0d
#define CS4384_VOL_A2 0x0e
#define CS4384_VOL_B2 0x0f
#define CS4384_MIX_PR3 0x10
#define CS4384_VOL_A3 0x11
#define CS4384_VOL_B3 0x12
#define CS4384_MIX_PR4 0x13
#define CS4384_VOL_A4 0x14
#define CS4384_VOL_B4 0x15
#define CS4384_CM_MODE 0x16
#endif /* CS4384_H_ */

18
examples/AN00247_xua_example_spdif_tx/src/cs5368.h Normal file
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// Copyright (c) 2017-2018, XMOS Ltd, All rights reserved
#ifndef _CS5368_H_
#define _CS5368_H_
//Address on I2C bus
#define CS5368_I2C_ADDR (0x4C)
//Register Addresess
#define CS5368_CHIP_REV 0x00
#define CS5368_GCTL_MDE 0x01
#define CS5368_OVFL_ST 0x02
#define CS5368_OVFL_MSK 0x03
#define CS5368_HPF_CTRL 0x04
#define CS5368_PWR_DN 0x06
#define CS5368_MUTE_CTRL 0x08
#define CS5368_SDO_EN 0x0a
#endif /* _CS5368_H_ */

135
examples/AN00247_xua_example_spdif_tx/src/hwsupport.xc Normal file
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// Copyright (c) 2016-2018, XMOS Ltd, All rights reserved
#include <platform.h>
#include <timer.h>
#include "xua.h"
#include "i2c_shared.h"
#include "cs5368.h"
#include "cs4384.h"
on tile [0] : struct r_i2c r_i2c = {XS1_PORT_4A};
/* General output port bit definitions */
#define P_GPIO_DSD_MODE (1 << 0) /* DSD mode select 0 = 8i/8o I2S, 1 = 8o DSD*/
#define P_GPIO_DAC_RST_N (1 << 1)
#define P_GPIO_USB_SEL0 (1 << 2)
#define P_GPIO_USB_SEL1 (1 << 3)
#define P_GPIO_VBUS_EN (1 << 4)
#define P_GPIO_PLL_SEL (1 << 5) /* 1 = CS2100, 0 = Phaselink clock source */
#define P_GPIO_ADC_RST_N (1 << 6)
#define P_GPIO_MCLK_FSEL (1 << 7) /* Select frequency on Phaselink clock. 0 = 24.576MHz for 48k, 1 = 22.5792MHz for 44.1k.*/
#define DAC_REGWRITE(reg, val) {data[0] = val; i2c_shared_master_write_reg(r_i2c, CS4384_I2C_ADDR, reg, data, 1);}
#define DAC_REGREAD(reg, val) {i2c_shared_master_read_reg(r_i2c, CS4384_I2C_ADDR, reg, val, 1);}
#define ADC_REGWRITE(reg, val) {data[0] = val; i2c_shared_master_write_reg(r_i2c, CS5368_I2C_ADDR, reg, data, 1);}
out port p_gpio = on tile[0]:XS1_PORT_8C;
void AudioHwConfig(unsigned samFreq, unsigned mClk, unsigned dsdMode,
unsigned sampRes_DAC, unsigned sampRes_ADC)
{
unsigned char data[1] = {0};
unsigned char gpioVal = 0;
/* Set master clock select appropriately and put ADC and DAC into reset */
if (mClk == MCLK_441)
{
gpioVal = P_GPIO_USB_SEL0 | P_GPIO_USB_SEL1;
}
else
{
gpioVal = P_GPIO_USB_SEL0 | P_GPIO_USB_SEL1 | P_GPIO_MCLK_FSEL;
}
p_gpio <: gpioVal;
/* Allow MCLK to settle */
delay_microseconds(20000);
/* Take ADC out of reset */
gpioVal |= P_GPIO_ADC_RST_N;
p_gpio <: gpioVal;
/* Configure ADC for I2S slave mode via I2C */
unsigned dif = 0, mode = 0;
dif = 0x01; /* I2S */
mode = 0x03; /* Slave mode all speeds */
/* Reg 0x01: (GCTL) Global Mode Control Register
* Bit[7]: CP-EN: Manages control-port mode
* Bit[6]: CLKMODE: Setting puts part in 384x mode
* Bit[5:4]: MDIV[1:0]: Set to 01 for /2
* Bit[3:2]: DIF[1:0]: Data Format: 0x01 for I2S, 0x02 for TDM
* Bit[1:0]: MODE[1:0]: Mode: 0x11 for slave mode
*/
ADC_REGWRITE(CS5368_GCTL_MDE, 0b10010000 | (dif << 2) | mode);
/* Reg 0x06: (PDN) Power Down Register */
/* Bit[7:6]: Reserved
* Bit[5]: PDN-BG: When set, this bit powers-own the bandgap reference
* Bit[4]: PDM-OSC: Controls power to internal oscillator core
* Bit[3:0]: PDN: When any bit is set all clocks going to that channel pair are turned off
*/
ADC_REGWRITE(CS5368_PWR_DN, 0b00000000);
/* Configure DAC with PCM values. Note 2 writes to mode control to enable/disable freeze/power down */
/* Take DAC out of reset */
gpioVal |= P_GPIO_DAC_RST_N;
p_gpio <: gpioVal;
delay_microseconds(500);
/* Mode Control 1 (Address: 0x02) */
/* bit[7] : Control Port Enable (CPEN) : Set to 1 for enable
* bit[6] : Freeze controls (FREEZE) : Set to 1 for freeze
* bit[5] : PCM/DSD Selection (DSD/PCM) : Set to 0 for PCM
* bit[4:1] : DAC Pair Disable (DACx_DIS) : All Dac Pairs enabled
* bit[0] : Power Down (PDN) : Powered down
*/
DAC_REGWRITE(CS4384_MODE_CTRL, 0b11000001);
/* PCM Control (Address: 0x03) */
/* bit[7:4] : Digital Interface Format (DIF) : 0b0001 for I2S up to 24bit
* bit[3:2] : Reserved
* bit[1:0] : Functional Mode (FM) : 0x00 - single-speed mode (4-50kHz)
* : 0x01 - double-speed mode (50-100kHz)
* : 0x10 - quad-speed mode (100-200kHz)
* : 0x11 - auto-speed detect (32 to 200kHz)
* (note, some Mclk/SR ratios not supported in auto)
*
*/
unsigned char regVal = 0;
if(samFreq < 50000)
regVal = 0b00010100;
else if(samFreq < 100000)
regVal = 0b00010101;
else //if(samFreq < 200000)
regVal = 0b00010110;
DAC_REGWRITE(CS4384_PCM_CTRL, regVal);
/* Mode Control 1 (Address: 0x02) */
/* bit[7] : Control Port Enable (CPEN) : Set to 1 for enable
* bit[6] : Freeze controls (FREEZE) : Set to 0 for freeze
* bit[5] : PCM/DSD Selection (DSD/PCM) : Set to 0 for PCM
* bit[4:1] : DAC Pair Disable (DACx_DIS) : All Dac Pairs enabled
* bit[0] : Power Down (PDN) : Not powered down
*/
DAC_REGWRITE(CS4384_MODE_CTRL, 0b10000000);
return;
}
void AudioHwInit()
{
/* Set USB Mux to micro-b */
/* ADC and DAC in reset */
p_gpio <: P_GPIO_USB_SEL0 | P_GPIO_USB_SEL1;
/* Init the i2c module */
i2c_shared_master_init(r_i2c);
}

88
examples/AN00247_xua_example_spdif_tx/src/xk-audio-216-mc.xn Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<Network xmlns="http://www.xmos.com" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.xmos.com http://www.xmos.com" ManuallySpecifiedRouting="true">
<Type>Board</Type>
<Name>XS2 MC Audio</Name>
<Declarations>
<Declaration>tileref tile[2]</Declaration>
<Declaration>tileref usb_tile</Declaration>
</Declarations>
<Packages>
<Package id="0" Type="XS2-UnA-512-FB236">
<Nodes>
<Node Id="0" InPackageId="0" Type="XS2-L16A-512" Oscillator="24MHz" SystemFrequency="500MHz" referencefrequency="100MHz">
<Boot>
<Source Location="SPI:bootFlash"/>
</Boot>
<Tile Number="0" Reference="tile[0]">
<Port Location="XS1_PORT_1B" Name="PORT_SQI_CS"/>
<Port Location="XS1_PORT_1C" Name="PORT_SQI_SCLK"/>
<Port Location="XS1_PORT_4B" Name="PORT_SQI_SIO"/>
<!-- Audio Ports -->
<Port Location="XS1_PORT_1A" Name="PORT_PLL_REF"/>
<Port Location="XS1_PORT_1F" Name="PORT_MCLK_IN"/>
<Port Location="XS1_PORT_1G" Name="PORT_I2S_LRCLK"/>
<Port Location="XS1_PORT_1H" Name="PORT_I2S_BCLK"/>
<Port Location="XS1_PORT_1M" Name="PORT_I2S_DAC0"/>
<port Location="XS1_PORT_1N" Name="PORT_I2S_DAC1"/>
<port Location="XS1_PORT_1O" Name="PORT_I2S_DAC2"/>
<port Location="XS1_PORT_1P" Name="PORT_I2S_DAC3"/>
<Port Location="XS1_PORT_1I" Name="PORT_I2S_ADC0"/>
<Port Location="XS1_PORT_1J" Name="PORT_I2S_ADC1"/>
<Port Location="XS1_PORT_1K" Name="PORT_I2S_ADC2"/>
<Port Location="XS1_PORT_1L" Name="PORT_I2S_ADC3"/>
<Port Location="XS1_PORT_4A" Name="PORT_I2C"/>
<Port Location="XS1_PORT_1M" Name="PORT_DSD_DAC0"/>
<port Location="XS1_PORT_1N" Name="PORT_DSD_DAC1"/>
<Port Location="XS1_PORT_1G" Name="PORT_DSD_CLK"/>
<Port Location="XS1_PORT_1E" Name="PORT_ADAT_OUT"/>--> <!-- D: COAX E: OPT -->
<Port Location="XS1_PORT_1D" Name="PORT_SPDIF_OUT"/>--> <!-- D: COAX E: OPT -->
</Tile>
<Tile Number="1" Reference="tile[1]">
<!-- USB intended to run on this tile -->
<!-- Ports for USB feedback calculation -->
<Port Location="XS1_PORT_16B" Name="PORT_MCLK_COUNT"/>
<Port Location="XS1_PORT_1L" Name="PORT_MCLK_IN_USB"/>
<!-- Audio Ports -->
<Port Location="XS1_PORT_1M" Name="PORT_MIDI_IN"/>
<Port Location="XS1_PORT_1N" Name="PORT_MIDI_OUT"/>
<Port Location="XS1_PORT_1O" Name="PORT_ADAT_IN"/>--> <!-- P: COAX O: OPT -->
<Port Location="XS1_PORT_1P" Name="PORT_SPDIF_IN"/>--> <!-- P: COAX O: OPT -->
</Tile>
</Node>
<Node Id="1" InPackageId="1" Type="periph:XS1-SU" Reference="usb_tile" Oscillator="24MHz">
</Node>
</Nodes>
<Links>
<Link Encoding="5wire">
<LinkEndpoint NodeId="0" Link="8" Delays="52clk,52clk"/>
<LinkEndpoint NodeId="1" Link="XL0" Delays="1clk,1clk"/>
</Link>
</Links>
</Package>
</Packages>
<Nodes>
<Node Id="2" Type="device:" RoutingId="0x8000">
<Service Id="0" Proto="xscope_host_data(chanend c);">
<Chanend Identifier="c" end="3"/>
</Service>
</Node>
</Nodes>
<Links>
<Link Encoding="2wire" Delays="4,4" Flags="XSCOPE">
<LinkEndpoint NodeId="0" Link="XL0"/>
<LinkEndpoint NodeId="2" Chanend="1"/>
</Link>
</Links>
<ExternalDevices>
<Device NodeId="0" Tile="0" Class="SQIFlash" Name="bootFlash" Type="S25FL116K">
<Attribute Name="PORT_SQI_CS" Value="PORT_SQI_CS"/>
<Attribute Name="PORT_SQI_SCLK" Value="PORT_SQI_SCLK"/>
<Attribute Name="PORT_SQI_SIO" Value="PORT_SQI_SIO"/>
</Device>
</ExternalDevices>
<JTAGChain>
<JTAGDevice NodeId="0"/>
<JTAGDevice NodeId="1"/>
</JTAGChain>
</Network>

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examples/AN00247_xua_example_spdif_tx/src/xua_conf.h Normal file
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// Copyright (c) 2017-2018, XMOS Ltd, All rights reserved
#ifndef _XUA_CONF_H_
#define _XUA_CONF_H_
#define NUM_USB_CHAN_OUT 2
#define NUM_USB_CHAN_IN 0
#define I2S_CHANS_DAC 0
#define I2S_CHANS_ADC 0
#define MCLK_441 (512 * 44100)
#define MCLK_48 (512 * 48000)
#define MIN_FREQ 48000
#define MAX_FREQ 48000
#define EXCLUDE_USB_AUDIO_MAIN
#define XUA_SPDIF_TX_EN 1
#define SPDIF_TX_INDEX 0
#define VENDOR_STR "XMOS"
#define VENDOR_ID 0x20B1
#define PRODUCT_STR_A2 "XUA SPDIF Example"
#define PRODUCT_STR_A1 "XUA SPDIF Example"
#define PID_AUDIO_1 1
#define PID_AUDIO_2 2
#define AUDIO_CLASS 2
#define AUDIO_CLASS_FALLBACK 0
#define BCD_DEVICE 0x1234
#define XUA_DFU_EN 0
#endif

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examples/AN00247_xua_example_spdif_tx/src/xud_conf.h Normal file
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// Copyright (c) 2017-2018, XMOS Ltd, All rights reserved
#include "xua_conf.h"
/* TODO */
#define XUD_UAC_NUM_USB_CHAN_OUT NUM_USB_CHAN_OUT
#define XUD_UAC_NUM_USB_CHAN_IN NUM_USB_CHAN_IN