74 lines
2.2 KiB
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74 lines
2.2 KiB
ReStructuredText
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Channel Counts and Sample Rates
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===============================
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The codebase is fully configurable in relation to channel counts and sample rates.
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Practical limitations of these are normally based on USB packet size restrictions and I/O
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availablity.
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For example, the maximum packet size for high-speed USB is 1024 bytes, limiting the channel count
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to 10 channels for a device running at 192kHz with 32bit sample depth.
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The defines in :ref:`opt_channel_defines` set the channel counts exposed to the USB host.
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.. tabularcolumns:: lp{5cm}l
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.. _opt_channel_defines:
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.. list-table:: Channel count defines
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:header-rows: 1
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:widths: 20 80 20
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* - Define
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- Description
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- Default
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* - ``NUM_USB_CHAN_OUT``
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- Number of output channels the device advertises to the USB host
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- N/A (must be defined)
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* - ``NUM_USB_CHAN_IN``
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- Number of input channels the device advertises to the USB host
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- N/A (must be defined)
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Sample rates ranges are set by the defines in :ref:`opt_channel_sr_defines`. The codebase will
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automatically populate the device sample rate list with popular frequencies between the min and
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max values. All values are in Hz:
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.. tabularcolumns:: lp{5cm}l
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.. _opt_channel_sr_defines:
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.. list-table:: Sample rate defines
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:header-rows: 1
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:widths: 20 80 20
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* - Define
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- Description
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- Default
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* - ``MAX_FREQ``
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- Maximum supported sample rate (Hz)
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- ``192000``
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* - ``MIN_FREQ``
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- Minimum supported sample rate (Hz)
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- ``44100``
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* - ``DEFAULT_FREQ``
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- Starting frequency for the device after boot
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- ``MIN_FREQ``
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The codebase requires knowledge of the two master clock frequencies that will be present on the
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master-clock port(s). One for 44.1kHz, 88.2kHz etc and one for 48kHz, 96kHz etc. These are set
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using defines in :ref:`opt_channel_mc_defines`. All values are in Hz.
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.. tabularcolumns:: lp{5cm}l
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.. _opt_channel_mc_defines:
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.. list-table:: Master clock rate defines
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:header-rows: 1
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:widths: 20 80 20
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* - Define
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- Description
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- Default
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* - ``CLK_441``
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- Master clock defines for 44100 rates (Hz)
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- ``(256 * 44100)``
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* - ``MCLK_48``
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- Master clock defines for 48000 rates (Hz)
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- ``(256 * 48000)``
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