64 lines
1.6 KiB
ArmAsm
64 lines
1.6 KiB
ArmAsm
#include "xs1_kernel.h"
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#include "xs1_user.h"
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.global write_sswitch_reg_blind, "f{si}(ui,ui,ui)"
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.type write_sswitch_reg_blind, @function
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// r0 - coreid
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// r1 - reg
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// r2 - data
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.cc_top write_sswitch_reg_blind.function, write_sswitch_reg_blind
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.align 2
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write_sswitch_reg_blind:
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// Check range of coreid
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shr r3, r0, XS1_CHAN_ID_PROCESSOR_SIZE + XS1_CHAN_ID_NODE_SIZE
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bt r3, write_switch_reg_fail
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// Check range of reg
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shr r3, r1, 16
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bt r3, write_switch_reg_fail
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// Allocate channel end
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getr r3, XS1_RES_TYPE_CHANEND
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// Set destination
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ldc r11, XS1_RES_TYPE_CONFIG | (XS1_CT_SSCTRL << XS1_CHAN_ID_CHANNUM_SHIFT)
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// r0 - l
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// r1 - reg
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// r2 - data
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// r3 - chanend
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// r11 - low half of dest
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write_switch_reg:
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shl r0, r0, XS1_CHAN_ID_PROCESSOR_SHIFT
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or r0, r0, r11
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setd res[r3], r0
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// Send packet
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ldc r11, XS1_CT_WRITEC // Too big for outct immediate
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outct res[r3], r11
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mkmsk r0, 32
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shl r0, r0, 8
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shr r11, r1, 8
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or r0, r0, r11
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out res[r3], r0 // (0xffffff00) | (reg >> 8)
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outt res[r3], r1 // reg & 0xff
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out res[r3], r2
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outct res[r3], XS1_CT_END
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// Receive response
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freer res[r3]
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retsp 0
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write_switch_reg_fail:
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ldc r0, 0
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retsp 0
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.size write_sswitch_reg_blind, .-write_sswitch_reg_blind
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.cc_bottom write_sswitch_reg_blind.function
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.global write_sswitch_reg_blind.nstackwords
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.global write_sswitch_reg_blind.maxchanends
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.global write_sswitch_reg_blind.maxtimers
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.global write_sswitch_reg_blind.maxcores
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.set write_sswitch_reg_blind.nstackwords, 0
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.set write_sswitch_reg_blind.maxchanends, 1
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.set write_sswitch_reg_blind.maxtimers, 0
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.set write_sswitch_reg_blind.maxcores, 0
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