630 lines
15 KiB
Plaintext
Executable File
630 lines
15 KiB
Plaintext
Executable File
/**
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* @file audio.xc
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* @brief XMOS L1/L2 USB 2,0 Audio Reference Design. Audio Functions.
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* @author Ross Owen, XMOS Semiconductor Ltd
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*
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* This thread handles I2S and pars an additional SPDIF Tx thread. It forwards samples to the SPDIF Tx thread.
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* Additionally this thread handles clocking and CODEC/DAC/ADC config.
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**/
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#include <syscall.h>
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#include <platform.h>
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#include <xs1.h>
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#include <xclib.h>
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#include <print.h>
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#include "clocking.h"
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#include "audioports.h"
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#include "codec.h"
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#include "devicedefines.h"
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#include "SpdifTransmit.h"
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//#define RAMP_CHECK 1
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//#pragma xta command "analyse path i2s_output_l i2s_output_r"
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//#pragma xta command "set required - 2000 ns"
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//#pragma xta command "analyse path i2s_output_r i2s_output_l"
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//#pragma xta command "set required - 2000 ns"
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/* I2S Data I/O*/
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#if (I2S_CHANS_DAC != 0)
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extern buffered out port:32 p_i2s_dac[I2S_WIRES_DAC];
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#endif
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#if (I2S_CHANS_ADC != 0)
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extern buffered in port:32 p_i2s_adc[I2S_WIRES_ADC];
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#endif
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/* I2S LR/Bit clock I/O */
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#ifdef CODEC_SLAVE
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extern buffered out port:32 p_lrclk;
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extern buffered out port:32 p_bclk;
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#else
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extern in port p_lrclk;
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extern in port p_bclk;
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#endif
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/* Master clock input */
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extern port p_mclk;
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#ifdef SPDIF
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extern buffered out port:32 p_spdif_tx;
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#endif
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extern clock clk_audio_mclk;
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extern clock clk_audio_bclk;
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extern clock clk_mst_spd;
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extern void device_reboot(void);
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/* I2S delivery thread */
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#pragma unsafe arrays
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unsigned deliver(chanend c_out, chanend ?c_spd_out, unsigned divide, chanend ?c_dig_rx)
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{
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unsigned sample;
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#if NUM_USB_CHAN_OUT > 0
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unsigned samplesOut[NUM_USB_CHAN_OUT];
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#endif
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#if NUM_USB_CHAN_IN > 0
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unsigned samplesIn[NUM_USB_CHAN_IN];
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unsigned samplesInPrev[NUM_USB_CHAN_IN];
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#endif
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unsigned tmp;
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unsigned index;
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#ifdef RAMP_CHECK
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unsigned prev=0;
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int started = 0;
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#endif
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#if NUM_USB_CHAN_IN > 0
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for (int i=0;i<NUM_USB_CHAN_IN;i++)
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{
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samplesIn[i] = 0;
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samplesInPrev[i] = 0;
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}
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#endif
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outuint(c_out, 0);
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/* Check for sample freq change or new samples from mixer*/
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if(testct(c_out))
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{
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inct(c_out);
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return inuint(c_out);
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}
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else
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{
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#ifndef MIXER // Interfaces straight to decouple()
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(void) inuint(c_out);
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#if NUM_USB_CHAN_IN > 0
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#pragma loop unroll
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for(int i = 0; i < NUM_USB_CHAN_IN; i++)
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{
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outuint(c_out, samplesIn[i]);
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}
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#endif
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#if NUM_USB_CHAN_OUT > 0
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#pragma loop unroll
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for(int i = 0; i < NUM_USB_CHAN_OUT; i++)
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{
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samplesOut[i] = inuint(c_out);
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}
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#endif
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#else
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#pragma loop unroll
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for(int i = 0; i < NUM_USB_CHAN_OUT; i++)
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{
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int tmp = inuint(c_out);
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#if defined(OUT_VOLUME_IN_MIXER) && defined(OUT_VOLUME_AFTER_MIX)
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tmp<<=3;
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#endif
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samplesOut[i] = tmp;
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}
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#pragma loop unroll
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for(int i = 0; i < NUM_USB_CHAN_IN; i++)
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{
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outuint(c_out, samplesIn[i]);
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}
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#endif
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}
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#ifdef CODEC_SLAVE
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/* Clear I2S port buffers */
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clearbuf(p_lrclk);
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#if (I2S_CHANS_DAC != 0)
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for(int i = 0; i < I2S_WIRES_DAC; i++)
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{
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clearbuf(p_i2s_dac[i]);
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}
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#endif
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#if (I2S_CHANS_ADC != 0)
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for(int i = 0; i < I2S_WIRES_ADC; i++)
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{
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clearbuf(p_i2s_adc[i]);
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}
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#endif
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if(divide == 1)
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{
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p_lrclk <: 0 @ tmp;
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tmp += 30;
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/* Prefill the ports so data starts to be input */
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#if (I2S_CHANS_DAC != 0)
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#pragma loop unroll
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for(int i = 0; i < I2S_WIRES_DAC; i++)
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{
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p_i2s_dac[i] @ tmp <: 0;
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}
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#endif
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p_lrclk @ tmp <: 0x7FFFFFFF;
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#if (I2S_CHANS_ADC != 0)
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p_i2s_adc[0] @ (tmp - 1) :> void;
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#endif
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#if (I2S_CHANS_ADC != 0)
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#pragma loop unroll
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for(int i = 0; i < I2S_WIRES_ADC; i++)
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{
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clearbuf(p_i2s_adc[i]);
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}
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#endif
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}
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else
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{
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clearbuf(p_bclk);
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#if (I2S_CHANS_DAC != 0)
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/* Prefill the ports so data is input in advance */
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for(int i = 0; i < I2S_WIRES_DAC; i++)
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{
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p_i2s_dac[i] <: 0;
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}
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#endif
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p_lrclk <: 0x7FFFFFFF;
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p_bclk <: 0xAAAAAAAA;
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p_bclk <: 0xAAAAAAAA;
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}
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#else
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/* CODEC is master */
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/* Wait for LRCLK edge */
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p_lrclk when pinseq(0) :> void;
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p_lrclk when pinseq(1) :> void;
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p_lrclk when pinseq(0) :> void;
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p_lrclk when pinseq(1) :> void;
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p_lrclk when pinseq(0) :> void @ tmp;
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tmp += 33;
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#if (I2S_CHANS_DAC != 0)
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#pragma loop unroll
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for(int i = 0; i < I2S_WIRES_DAC; i++)
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{
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p_i2s_dac[i] @ tmp <: 0;
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}
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#endif
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p_i2s_adc[0] @ tmp - 1 :> void;
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#pragma loop unroll
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for(int i = 0; i < I2S_WIRES_ADC; i++)
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{
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clearbuf(p_i2s_adc[i]);
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}
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/* TODO In master mode, the i/o loop assumes L/RCLK = 32bit clocks. We should check this every interation
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* and resync if we got a bclk glitch */
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#endif
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/* Main Audio I/O loop */
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while (1)
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{
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outuint(c_out, 0);
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/* Check for sample freq change or new samples from mixer*/
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if(testct(c_out))
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{
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inct(c_out);
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return inuint(c_out);
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}
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else
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{
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#ifndef MIXER // Interfaces straight to decouple()
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(void) inuint(c_out);
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#if NUM_USB_CHAN_IN > 0
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#pragma loop unroll
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for(int i = 0; i < NUM_USB_CHAN_IN; i++)
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{
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outuint(c_out, samplesIn[i]);
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}
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#endif
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#if NUM_USB_CHAN_OUT > 0
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#pragma loop unroll
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for(int i = 0; i < NUM_USB_CHAN_OUT; i++)
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{
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samplesOut[i] = inuint(c_out);
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}
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#endif
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#else
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#pragma loop unroll
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for(int i = 0; i < NUM_USB_CHAN_OUT; i++)
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{
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int tmp = inuint(c_out);
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#if defined(OUT_VOLUME_IN_MIXER) && defined(OUT_VOLUME_AFTER_MIX)
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tmp<<=3;
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#endif
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samplesOut[i] = tmp;
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}
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#pragma loop unroll
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for(int i = 0; i < NUM_USB_CHAN_IN; i++)
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{
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outuint(c_out, samplesIn[i]);
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}
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#endif
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}
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#if defined(SPDIF_RX) || defined(ADAT_RX)
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inuint(c_dig_rx);
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#endif
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#ifdef SPDIF_RX
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asm("ldw %0, dp[g_digData]":"=r"(samplesIn[SPDIF_RX_INDEX + 0]));
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asm("ldw %0, dp[g_digData+4]":"=r"(samplesIn[SPDIF_RX_INDEX + 1]));
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#endif
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#ifdef ADAT_RX
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asm("ldw %0, dp[g_digData+8]":"=r"(samplesIn[ADAT_RX_INDEX + 0]));
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asm("ldw %0, dp[g_digData+12]":"=r"(samplesIn[ADAT_RX_INDEX+ 1]));
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asm("ldw %0, dp[g_digData+16]":"=r"(samplesIn[ADAT_RX_INDEX + 2]));
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asm("ldw %0, dp[g_digData+20]":"=r"(samplesIn[ADAT_RX_INDEX + 3]));
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asm("ldw %0, dp[g_digData+24]":"=r"(samplesIn[ADAT_RX_INDEX + 4]));
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asm("ldw %0, dp[g_digData+28]":"=r"(samplesIn[ADAT_RX_INDEX + 5]));
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asm("ldw %0, dp[g_digData+32]":"=r"(samplesIn[ADAT_RX_INDEX + 6]));
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asm("ldw %0, dp[g_digData+36]":"=r"(samplesIn[ADAT_RX_INDEX + 7]));
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#endif
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#if defined(SPDIF_RX) || defined(ADAT_RX)
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/* Request digital data (with prefill) */
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outuint(c_dig_rx, 0);
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#endif
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tmp = 0;
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#pragma xta endpoint "i2s_output_l"
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#if (I2S_CHANS_DAC != 0) && (NUM_USB_CHAN_OUT != 0)
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#pragma loop unroll
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for(int i = 0; i < I2S_CHANS_DAC; i+=2)
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{
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p_i2s_dac[tmp++] <: bitrev(samplesOut[i]); /* Output LEFT sample to DAC */
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}
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#endif
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#ifdef CODEC_SLAVE
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/* Generate clocks LR Clock low - LEFT */
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switch (divide)
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{
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case 8:
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/* LR clock delayed by one clock, This is so MSB is output on the falling edge of BCLK
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* after the falling edge on which LRCLK was toggled. (see I2S spec) */
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p_lrclk <: 0x80000000;
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p_bclk <: 0xF0F0F0F0;
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p_bclk <: 0xF0F0F0F0;
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p_bclk <: 0xF0F0F0F0;
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p_bclk <: 0xF0F0F0F0;
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p_bclk <: 0xF0F0F0F0;
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p_bclk <: 0xF0F0F0F0;
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p_bclk <: 0xF0F0F0F0;
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p_bclk <: 0xF0F0F0F0;
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break;
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case 4:
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p_lrclk <: 0x80000000;
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p_bclk <: 0xCCCCCCCC;
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p_bclk <: 0xCCCCCCCC;
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p_bclk <: 0xCCCCCCCC;
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p_bclk <: 0xCCCCCCCC;
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break;
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case 2:
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p_lrclk <: 0x80000000;
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p_bclk <: 0xAAAAAAAA;
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p_bclk <: 0xAAAAAAAA;
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break;
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case 1:
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p_lrclk <: 0x80000000;
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break;
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}
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#endif
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#if (I2S_CHANS_ADC != 0)
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/* Input prevous R sample into R in buffer */
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index = 0;
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#pragma loop unroll
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for(int i = 1; i < I2S_CHANS_ADC; i += 2)
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{
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p_i2s_adc[index++] :> sample;
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#if NUM_USB_CHAN_IN > 0
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samplesIn[i] = bitrev(sample);
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/* Store the previous left in left */
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samplesIn[i-1] = samplesInPrev[i];
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#endif
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}
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#endif
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#if defined(SPDIF) && (NUM_USB_CHAN_OUT > 0)
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outuint(c_spd_out, samplesOut[SPDIF_TX_INDEX]); /* Forward sample to SPDIF txt thread */
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sample = samplesOut[SPDIF_TX_INDEX + 1];
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outuint(c_spd_out, sample); /* Forward sample to SPDIF txt thread */
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#ifdef RAMP_CHECK
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sample >>= 8;
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if (started<10000) {
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if (sample == prev+1)
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started++;
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}
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else
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if (sample != prev+1 && sample != 0) {
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printintln(prev);
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printintln(sample);
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printintln(prev-sample+1);
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}
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prev = sample;
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#endif
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#endif
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tmp = 0;
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#pragma xta endpoint "i2s_output_r"
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#if (I2S_CHANS_DAC != 0) && (NUM_USB_CHAN_OUT != 0)
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#pragma loop unroll
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for(int i = 1; i < I2S_CHANS_DAC; i+=2)
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{
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p_i2s_dac[tmp++] <: bitrev(samplesOut[i]); /* Output RIGHT sample to DAC */
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}
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#endif
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#ifdef CODEC_SLAVE
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/* Clock out data (and LR clock) */
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switch (divide)
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{
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case 8:
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p_lrclk <: 0x7FFFFFFF;
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p_bclk <: 0xF0F0F0F0;
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p_bclk <: 0xF0F0F0F0;
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p_bclk <: 0xF0F0F0F0;
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p_bclk <: 0xF0F0F0F0;
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p_bclk <: 0xF0F0F0F0;
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p_bclk <: 0xF0F0F0F0;
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p_bclk <: 0xF0F0F0F0;
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p_bclk <: 0xF0F0F0F0;
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break;
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case 4:
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p_lrclk <: 0x7FFFFFFF;
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p_bclk <: 0xCCCCCCCC;
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p_bclk <: 0xCCCCCCCC;
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p_bclk <: 0xCCCCCCCC;
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p_bclk <: 0xCCCCCCCC;
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break;
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case 2:
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p_lrclk <: 0x7FFFFFFF;
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p_bclk <: 0xAAAAAAAA;
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p_bclk <: 0xAAAAAAAA;
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break;
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case 1:
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p_lrclk <: 0x7FFFFFFF;
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break;
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}
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#endif
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#if (I2S_CHANS_ADC != 0)
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/* Input previous L ADC sample */
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index = 0;
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#pragma loop unroll
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for(int i = 1; i < I2S_CHANS_ADC; i += 2)
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{
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p_i2s_adc[index++] :> sample;
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#if NUM_USB_CHAN_IN > 0
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samplesInPrev[i] = bitrev(sample);
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#endif
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}
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#endif
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}
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return 0;
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}
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/* This function is a dummy version of the deliver thread that does not
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connect to the codec ports. It is used during DFU reset. */
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static unsigned dummy_deliver(chanend c_out) {
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while (1)
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{
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outuint(c_out, 0);
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/* Check for sample freq change or new samples from mixer*/
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if(testct(c_out))
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{
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inct(c_out);
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return inuint(c_out);
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}
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else
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{
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#ifndef MIXER // Interfaces straight to decouple()
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(void) inuint(c_out);
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#pragma loop unroll
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for(int i = 0; i < NUM_USB_CHAN_IN; i++)
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{
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outuint(c_out, 0);
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}
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#pragma loop unroll
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for(int i = 0; i < NUM_USB_CHAN_OUT; i++)
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{
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(void) inuint(c_out);
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}
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#else
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#pragma loop unroll
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for(int i = 0; i < NUM_USB_CHAN_OUT; i++)
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{
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(void) inuint(c_out);
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}
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#pragma loop unroll
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for(int i = 0; i < NUM_USB_CHAN_IN; i++)
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{
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outuint(c_out, 0);
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}
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#endif
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}
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}
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return 0;
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}
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void audio(chanend c_mix_out, chanend ?c_dig_rx, chanend ?c_config)
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{
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#ifdef SPDIF
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chan c_spdif_out;
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#endif
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unsigned curSamFreq = DEFAULT_FREQ;
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unsigned mClk;
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unsigned divide;
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unsigned firstRun = 1;
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#ifdef SPDIF
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SpdifTransmitPortConfig(p_spdif_tx, clk_mst_spd, p_mclk);
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#endif
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/* Initialise master clock generation */
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ClockingInit(c_config);
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/* Perform required CODEC/ADC/DAC initialisation */
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CodecInit(c_config);
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while(1)
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{
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|
|
/* Calculate what master clock we should be using */
|
|
if ((curSamFreq % 22050) == 0)
|
|
{
|
|
mClk = MCLK_441;
|
|
}
|
|
else if ((curSamFreq % 24000) == 0)
|
|
{
|
|
mClk = MCLK_48;
|
|
}
|
|
|
|
/* Calculate divide required for bit clock e.g. 11.289600 / (176400 * 64) = 1 */
|
|
divide = mClk / ( curSamFreq * 64 );
|
|
|
|
/* Configure clocking for required master clock */
|
|
ClockingConfig(mClk, c_config);
|
|
|
|
if(!firstRun)
|
|
{
|
|
/* TODO wait for good mclk instead of delay */
|
|
/* No delay for DFU modes */
|
|
if ((curSamFreq != AUDIO_REBOOT_FROM_DFU) && (curSamFreq != AUDIO_STOP_FOR_DFU))
|
|
{
|
|
timer t;
|
|
unsigned time;
|
|
t :> time;
|
|
t when timerafter(time+AUDIO_PLL_LOCK_DELAY) :> void;
|
|
|
|
/* Handshake back */
|
|
outct(c_mix_out, XS1_CT_END);
|
|
}
|
|
}
|
|
firstRun = 0;
|
|
|
|
/* Configure CODEC/DAC/ADC for SampleFreq/MClk */
|
|
CodecConfig(curSamFreq, mClk, c_config);
|
|
|
|
/* Configure audio ports */
|
|
ConfigAudioPorts(divide);
|
|
|
|
par
|
|
{
|
|
|
|
#ifdef SPDIF
|
|
{ //set_thread_fast_mode_on();
|
|
SpdifTransmit(p_spdif_tx, c_spdif_out);
|
|
}
|
|
#endif
|
|
|
|
{
|
|
#ifdef SPDIF
|
|
/* Communicate master clock and sample freq to S/PDIF thread */
|
|
outuint(c_spdif_out, curSamFreq);
|
|
outuint(c_spdif_out, mClk);
|
|
#endif
|
|
|
|
curSamFreq = deliver(c_mix_out,
|
|
#ifdef SPDIF
|
|
c_spdif_out,
|
|
#else
|
|
null,
|
|
#endif
|
|
divide, c_dig_rx);
|
|
|
|
// Currently no more audio will happen after this point
|
|
if (curSamFreq == AUDIO_STOP_FOR_DFU)
|
|
{
|
|
outct(c_mix_out, XS1_CT_END);
|
|
|
|
while (1)
|
|
{
|
|
|
|
curSamFreq = dummy_deliver(c_mix_out);
|
|
|
|
if (curSamFreq == AUDIO_START_FROM_DFU)
|
|
{
|
|
outct(c_mix_out, XS1_CT_END);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
|
|
#ifdef SPDIF
|
|
/* Notify S/PDIF thread of impending new freq... */
|
|
outct(c_spdif_out, XS1_CT_END);
|
|
#endif
|
|
}
|
|
}
|
|
}
|
|
}
|