281 lines
10 KiB
Plaintext
Executable File
281 lines
10 KiB
Plaintext
Executable File
#include <xs1.h>
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#include <assert.h>
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#include <platform.h>
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#include <print.h>
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#include <stdio.h>
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#include "i2c.h"
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#include "xua.h"
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#define DEBUG_UNIT AUDIO_CFG
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#define DEBUG_PRINT_ENABLE_AUDIO_CFG 1
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#include "debug_print.h"
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// TLV320DAC3101 Device I2C Address
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#define DAC3101_I2C_DEVICE_ADDR 0x18
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// TLV320DAC3101 Register Addresses
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// Page 0
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#define DAC3101_PAGE_CTRL 0x00 // Register 0 - Page Control
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#define DAC3101_SW_RST 0x01 // Register 1 - Software Reset
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#define DAC3101_CLK_GEN_MUX 0x04 // Register 4 - Clock-Gen Muxing
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#define DAC3101_PLL_P_R 0x05 // Register 5 - PLL P and R Values
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#define DAC3101_PLL_J 0x06 // Register 6 - PLL J Value
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#define DAC3101_PLL_D_MSB 0x07 // Register 7 - PLL D Value (MSB)
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#define DAC3101_PLL_D_LSB 0x08 // Register 8 - PLL D Value (LSB)
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#define DAC3101_NDAC_VAL 0x0B // Register 11 - NDAC Divider Value
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#define DAC3101_MDAC_VAL 0x0C // Register 12 - MDAC Divider Value
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#define DAC3101_DOSR_VAL_LSB 0x0E // Register 14 - DOSR Divider Value (LS Byte)
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#define DAC3101_CLKOUT_MUX 0x19 // Register 25 - CLKOUT MUX
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#define DAC3101_CLKOUT_M_VAL 0x1A // Register 26 - CLKOUT M_VAL
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#define DAC3101_CODEC_IF 0x1B // Register 27 - CODEC Interface Control
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#define DAC3101_DAC_DAT_PATH 0x3F // Register 63 - DAC Data Path Setup
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#define DAC3101_DAC_VOL 0x40 // Register 64 - DAC Vol Control
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#define DAC3101_DACL_VOL_D 0x41 // Register 65 - DAC Left Digital Vol Control
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#define DAC3101_DACR_VOL_D 0x42 // Register 66 - DAC Right Digital Vol Control
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#define DAC3101_GPIO1_IO 0x33 // Register 51 - GPIO1 In/Out Pin Control
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// Page 1
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#define DAC3101_HP_DRVR 0x1F // Register 31 - Headphone Drivers
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#define DAC3101_SPK_AMP 0x20 // Register 32 - Class-D Speaker Amp
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#define DAC3101_HP_DEPOP 0x21 // Register 33 - Headphone Driver De-pop
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#define DAC3101_DAC_OP_MIX 0x23 // Register 35 - DAC_L and DAC_R Output Mixer Routing
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#define DAC3101_HPL_VOL_A 0x24 // Register 36 - Analog Volume to HPL
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#define DAC3101_HPR_VOL_A 0x25 // Register 37 - Analog Volume to HPR
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#define DAC3101_SPKL_VOL_A 0x26 // Register 38 - Analog Volume to Left Speaker
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#define DAC3101_SPKR_VOL_A 0x27 // Register 39 - Analog Volume to Right Speaker
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#define DAC3101_HPL_DRVR 0x28 // Register 40 - Headphone Left Driver
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#define DAC3101_HPR_DRVR 0x29 // Register 41 - Headphone Right Driver
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#define DAC3101_SPKL_DRVR 0x2A // Register 42 - Left Class-D Speaker Driver
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#define DAC3101_SPKR_DRVR 0x2B // Register 43 - Right Class-D Speaker Driver
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// TLV320DAC3101 easy register access defines
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#define DAC3101_REGWRITE(reg, val) {i_i2c.write_reg(DAC3101_I2C_DEVICE_ADDR, reg, val);}
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static void set_node_pll_reg(tileref tile_ref, unsigned reg_val){
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write_sswitch_reg(get_tile_id(tile_ref), XS1_SSWITCH_PLL_CTL_NUM, reg_val);
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}
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// Nominal setting is ref div = 25, fb_div = 1024, op_div = 2
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// PCF Freq 0.96MHz
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enum clock_nudge{
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PLL_SLOWER = -1,
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PLL_NOMINAL = 0,
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PLL_FASTER = 1
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};
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#define PLL_LOW 0xC003FE18 // This is 3.069MHz
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#define PLL_NOM 0xC003FF18 // This is 3.072MHz
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#define PLL_HIGH 0xC0040018 // This is 3.075MHz
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on tile[0]: out port p_leds = XS1_PORT_4F;
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int old_nudge = 0;
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void pll_nudge(int nudge) {
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if (nudge > 0){
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set_node_pll_reg(tile[0], PLL_HIGH);
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p_leds <: 0xf;
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}
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else if (nudge < 0){
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set_node_pll_reg(tile[0], PLL_LOW);
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p_leds <: 0xf;
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}
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else {
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p_leds <: 0x0;
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}
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set_node_pll_reg(tile[0], PLL_NOM);
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//if(nudge != old_nudge && nudge){debug_printf("nudge: %d\n", nudge); }old_nudge = nudge;
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}
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void setup_audio_gpio(out port p_gpio){
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// Reset DAC and disable MUTE
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p_gpio <: 0x0;
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delay_milliseconds(1);
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p_gpio <: 0x1;
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delay_milliseconds(1);
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}
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void AudioHwConfigure(unsigned samFreq, client i2c_master_if i_i2c)
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{
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// Wait for 2ms because we apply reset for 1ms from other tile
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delay_milliseconds(2);
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// Set register page to 0
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DAC3101_REGWRITE(DAC3101_PAGE_CTRL, 0x00);
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// Initiate SW reset (PLL is powered off as part of reset)
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DAC3101_REGWRITE(DAC3101_SW_RST, 0x01);
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// so I've got 24MHz in to PLL, I want 24.576MHz or 22.5792MHz out.
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// I will always be using fractional-N (D != 0) so we must set R = 1
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// PLL_CLKIN/P must be between 10 and 20MHz so we must set P = 2
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// PLL_CLK = CLKIN * ((RxJ.D)/P)
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// We know R = 1, P = 2.
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// PLL_CLK = CLKIN * (J.D / 2)
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// For 24.576MHz:
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// J = 8
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// D = 1920
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// So PLL_CLK = 24 * (8.192/2) = 24 x 4.096 = 98.304MHz
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// Then:
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// NDAC = 4
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// MDAC = 4
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// DOSR = 128
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// So:
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// DAC_CLK = PLL_CLK / 4 = 24.576MHz.
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// DAC_MOD_CLK = DAC_CLK / 4 = 6.144MHz.
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// DAC_FS = DAC_MOD_CLK / 128 = 48kHz.
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// For 22.5792MHz:
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// J = 7
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// D = 5264
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// So PLL_CLK = 24 * (7.5264/2) = 24 x 3.7632 = 90.3168MHz
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// Then:
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// NDAC = 4
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// MDAC = 4
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// DOSR = 128
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// So:
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// DAC_CLK = PLL_CLK / 4 = 22.5792MHz.
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// DAC_MOD_CLK = DAC_CLK / 4 = 5.6448MHz.
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// DAC_FS = DAC_MOD_CLK / 128 = 44.1kHz.
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#if XUA_ADAPTIVE
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//Set nominal clock speed on PLL
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write_sswitch_reg(get_tile_id(tile[0]), XS1_SSWITCH_PLL_CTL_NUM, PLL_NOM);
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// We are assuming 48kHz family only and we generate MCLK
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// Set PLL J Value to 7
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DAC3101_REGWRITE(DAC3101_PLL_J, 0x07);
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// Set PLL D to 0 ...
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// Set PLL D MSB Value to 0x00
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DAC3101_REGWRITE(DAC3101_PLL_D_MSB, 0x07);
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// Set PLL D LSB Value to 0x00
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DAC3101_REGWRITE(DAC3101_PLL_D_LSB, 0x80);
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delay_milliseconds(1);
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// Set PLL_CLKIN = BCLK (device pin), CODEC_CLKIN = PLL_CLK (generated on-chip)
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DAC3101_REGWRITE(DAC3101_CLK_GEN_MUX, 0x07);
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// Set PLL P and R values and power up.
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DAC3101_REGWRITE(DAC3101_PLL_P_R, 0x94);
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// Set NDAC clock divider to 2 and power up.
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DAC3101_REGWRITE(DAC3101_NDAC_VAL, 0x82);
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// Set MDAC clock divider to 7 and power up.
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DAC3101_REGWRITE(DAC3101_MDAC_VAL, 0x87);
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// Set OSR clock divider to 128.
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DAC3101_REGWRITE(DAC3101_DOSR_VAL_LSB, 0x80);
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#else
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/* Sample frequency dependent register settings */
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if ((samFreq % 11025) == 0)
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{
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// MCLK = 22.5792MHz (44.1,88.2,176.4kHz)
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// Set PLL J Value to 7
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DAC3101_REGWRITE(DAC3101_PLL_J, 0x07);
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// Set PLL D to 5264 ... (0x1490)
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// Set PLL D MSB Value to 0x14
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DAC3101_REGWRITE(DAC3101_PLL_D_MSB, 0x14);
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// Set PLL D LSB Value to 0x90
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DAC3101_REGWRITE(DAC3101_PLL_D_LSB, 0x90);
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}
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else if ((samFreq % 8000) == 0)
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{
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// MCLK = 24.576MHz (48,96,192kHz)
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// Set PLL J Value to 8
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DAC3101_REGWRITE(DAC3101_PLL_J, 0x08);
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// Set PLL D to 1920 ... (0x780)
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// Set PLL D MSB Value to 0x07
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DAC3101_REGWRITE(DAC3101_PLL_D_MSB, 0x07);
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// Set PLL D LSB Value to 0x80
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DAC3101_REGWRITE(DAC3101_PLL_D_LSB, 0x80);
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}
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else
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{
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//debug_printf("Unrecognised sample freq of %d in ConfigCodec\n", samFreq);
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}
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delay_milliseconds(1);
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// Set PLL_CLKIN = MCLK (device pin), CODEC_CLKIN = PLL_CLK (generated on-chip)
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DAC3101_REGWRITE(DAC3101_CLK_GEN_MUX, 0x03);
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// Set PLL P and R values and power up.
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DAC3101_REGWRITE(DAC3101_PLL_P_R, 0xA1);
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// Set NDAC clock divider to 4 and power up.
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DAC3101_REGWRITE(DAC3101_NDAC_VAL, 0x84);
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// Set MDAC clock divider to 4 and power up.
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DAC3101_REGWRITE(DAC3101_MDAC_VAL, 0x84);
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// Set OSR clock divider to 128.
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DAC3101_REGWRITE(DAC3101_DOSR_VAL_LSB, 0x80);
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#endif
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// Set CLKOUT Mux to DAC_CLK
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DAC3101_REGWRITE(DAC3101_CLKOUT_MUX, 0x04);
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// Set CLKOUT M divider to 1 and power up.
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DAC3101_REGWRITE(DAC3101_CLKOUT_M_VAL, 0x81);
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// Set GPIO1 output to come from CLKOUT output.
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DAC3101_REGWRITE(DAC3101_GPIO1_IO, 0x10);
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// Set CODEC interface mode: I2S, 24 bit, slave mode (BCLK, WCLK both inputs).
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DAC3101_REGWRITE(DAC3101_CODEC_IF, 0x20);
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// Set register page to 1
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DAC3101_REGWRITE(DAC3101_PAGE_CTRL, 0x01);
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// Program common-mode voltage to mid scale 1.65V.
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DAC3101_REGWRITE(DAC3101_HP_DRVR, 0x14);
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// Program headphone-specific depop settings.
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// De-pop, Power on = 800 ms, Step time = 4 ms
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DAC3101_REGWRITE(DAC3101_HP_DEPOP, 0x4E);
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// Program routing of DAC output to the output amplifier (headphone/lineout or speaker)
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// LDAC routed to left channel mixer amp, RDAC routed to right channel mixer amp
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DAC3101_REGWRITE(DAC3101_DAC_OP_MIX, 0x44);
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// Unmute and set gain of output driver
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// Unmute HPL, set gain = 0 db
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DAC3101_REGWRITE(DAC3101_HPL_DRVR, 0x06);
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// Unmute HPR, set gain = 0 dB
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DAC3101_REGWRITE(DAC3101_HPR_DRVR, 0x06);
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// Unmute Left Class-D, set gain = 12 dB
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DAC3101_REGWRITE(DAC3101_SPKL_DRVR, 0x0C);
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// Unmute Right Class-D, set gain = 12 dB
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DAC3101_REGWRITE(DAC3101_SPKR_DRVR, 0x0C);
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// Power up output drivers
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// HPL and HPR powered up
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DAC3101_REGWRITE(DAC3101_HP_DRVR, 0xD4);
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// Power-up L and R Class-D drivers
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DAC3101_REGWRITE(DAC3101_SPK_AMP, 0xC6);
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// Enable HPL output analog volume, set = -9 dB
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DAC3101_REGWRITE(DAC3101_HPL_VOL_A, 0x92);
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// Enable HPR output analog volume, set = -9 dB
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DAC3101_REGWRITE(DAC3101_HPR_VOL_A, 0x92);
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// Enable Left Class-D output analog volume, set = -9 dB
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DAC3101_REGWRITE(DAC3101_SPKL_VOL_A, 0x92);
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// Enable Right Class-D output analog volume, set = -9 dB
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DAC3101_REGWRITE(DAC3101_SPKR_VOL_A, 0x92);
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delay_milliseconds(100);
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// Power up DAC
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// Set register page to 0
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DAC3101_REGWRITE(DAC3101_PAGE_CTRL, 0x00);
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// Power up DAC channels and set digital gain
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// Powerup DAC left and right channels (soft step enabled)
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DAC3101_REGWRITE(DAC3101_DAC_DAT_PATH, 0xD4);
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// DAC Left gain = 0dB
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DAC3101_REGWRITE(DAC3101_DACL_VOL_D, 0x00);
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// DAC Right gain = 0dB
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DAC3101_REGWRITE(DAC3101_DACR_VOL_D, 0x00);
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// Unmute digital volume control
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// Unmute DAC left and right channels
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DAC3101_REGWRITE(DAC3101_DAC_VOL, 0x00);
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i_i2c.shutdown();
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}
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//These are here just to silence compiler warnings
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void AudioHwInit(){}
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void AudioHwConfig(unsigned samFreq, unsigned mClk, unsigned dsdMode, unsigned sampRes_DAC, unsigned sampRes_ADC){} |