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Clockblock for L-series reset-port now declared on tile 0

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Ross Owen
2013-11-18 18:08:13 +00:00
parent 952e573bec
commit 06e9cf4d37
1 changed files with 1 additions and 1 deletions
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module_usb_audio/main.xc
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@@ -137,7 +137,7 @@ on tile[AUDIO_IO_TILE] : clock clk_mst_spd = XS1_CLKBLK_1;
on tile[0] : out port p_usb_rst = PORT_USB_RESET; on tile[0] : out port p_usb_rst = PORT_USB_RESET;
#endif #endif
/* L Series also needs a clock for this port */ /* L Series also needs a clock for this port */
clock clk = XS1_CLKBLK_4; on tile[0] : clock clk = XS1_CLKBLK_4;
#else #else
/* Reset port not required for SU1 due to built in Phy */ /* Reset port not required for SU1 due to built in Phy */
#define p_usb_rst null #define p_usb_rst null