deliver now sets bclk/dsd clk initial high. This was previously done in port config.

module_usb_audio/audio.xc

@@ -185,10 +185,11 @@ static inline void doI2SClocks(unsigned divide)
     if(dsdMode == DSD_MODE_DOP)
         underflowWord = 0xFA969600;
     else if(dsdMode == DSD_MODE_NATIVE)
+    {
         underflowWord = 0x96969696;
+    }
 #endif
 
-
     outuint(c_out, 0);
 
     /* Check for sample freq change or new samples from mixer*/
@@ -330,7 +331,6 @@ static inline void doI2SClocks(unsigned divide)
     {
         clearbuf(p_bclk);
 
-
 #if (I2S_CHANS_DAC != 0)
         /* Prefill the ports so data is input in advance */
         for(int i = 0; i < I2S_WIRES_DAC; i++)
@@ -338,7 +338,9 @@ static inline void doI2SClocks(unsigned divide)
             p_i2s_dac[i] <: 0;
         }
 #endif
-
+        /* b_clk must start high */
+        p_bclk <: 0x80000000;
+        sync(p_bclk);
 
         p_lrclk <: 0x7FFFFFFF; 
         doI2SClocks(divide);
@@ -346,6 +348,12 @@ static inline void doI2SClocks(unsigned divide)
     }
 #if (DSD_CHANS_DAC > 0)
     } /* if (!dsdMode) */
+    else
+    {
+        /* p_dsd_clk must start high */
+        p_dsd_clk <: 0x80000000;
+        //sync(p_dsd_clk);
+    }
 #endif
 #else          
     /* CODEC is master */

module_usb_audio/ports/audioports.xc

@@ -113,17 +113,9 @@ unsigned int divide)
     }
 #endif
 
-
     /* Start clock blocks ticking */
-    //start_clock(clk_audio_mclk);
     start_clock(clk_audio_bclk);
 
-    /* bclk initial state needs to be high  */
-    p_bclk <: 0xFFFFFFFF;
-
-    /* Pause until output completes */
-    sync(p_bclk);
-
 #else /* CODEC_MASTER */
 
     /* Stop bit and master clock blocks */