From 4962cebc9c12682974d7b58538dc2f00691e92da Mon Sep 17 00:00:00 2001 From: Ed Date: Fri, 5 Jan 2024 14:40:14 +0000 Subject: [PATCH] Comments only --- lib_xua/src/core/clocking/clockgen.xc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/lib_xua/src/core/clocking/clockgen.xc b/lib_xua/src/core/clocking/clockgen.xc index d67dcae1..1a11bd88 100644 --- a/lib_xua/src/core/clocking/clockgen.xc +++ b/lib_xua/src/core/clocking/clockgen.xc @@ -352,11 +352,11 @@ void SigmaDeltaTask(chanend c_sigma_delta, unsigned sdm_interval){ the first control value has been received. This avoids issues with channel lockup if two tasks (eg. init and SDM) try to write at the same time. */ - /* To be extra safe, spin on sw_pll_ptr until it has been initialised */ + /* To be extra safe, spin on sw_pll_ptr until it has been initialised by clockgen */ while(sw_pll_ptr == NULL); int f_error = 0; - int dco_setting = SW_PLL_SDM_CTRL_MID_24; // TODO Assume 24.576MHz? + int dco_setting = SW_PLL_SDM_CTRL_MID_24; // Assume 24.576MHz as initial clock unsafe { sw_pll_init_sigma_delta(&sw_pll_ptr->sdm_state); @@ -578,7 +578,7 @@ void clockGen ( streaming chanend ?c_spdif_rx, sw_pll_ptr = &sw_pll; } - unsigned sdm_interval = InitSWPLL(sw_pll, MCLK_48); + unsigned sdm_interval = InitSWPLL(sw_pll, MCLK_48); // Assume 24.576MHz initial clock par {