upgrade

lib_xua/api/xua_conf_default.h

@@ -748,7 +748,7 @@
         #define OUTPUT_FORMAT_COUNT 2
     #else
         /* Default format count is 3 (16bit, 24bit, DSD) */
-        #define OUTPUT_FORMAT_COUNT 3
+        #define OUTPUT_FORMAT_COUNT 2
     #endif
 #endif
 
@@ -782,7 +782,7 @@
     #if (NATIVE_DSD_FORMAT_NUM == 1)
         #define STREAM_FORMAT_OUTPUT_1_RESOLUTION_BITS      32  /* DSD requires 32bits */
     #else
-        #define STREAM_FORMAT_OUTPUT_1_RESOLUTION_BITS      24
+        #define STREAM_FORMAT_OUTPUT_1_RESOLUTION_BITS      32
     #endif
 #endif
 
@@ -796,7 +796,7 @@
 #if (NATIVE_DSD_FORMAT_NUM == 2)
         #define STREAM_FORMAT_OUTPUT_2_RESOLUTION_BITS      32  /* DSD requires 32bits */
     #else
-        #define STREAM_FORMAT_OUTPUT_2_RESOLUTION_BITS      16
+        #define STREAM_FORMAT_OUTPUT_2_RESOLUTION_BITS      24
     #endif
 #endif
 
@@ -980,7 +980,7 @@
  * Default: 1
  */
 #ifndef INPUT_FORMAT_COUNT
-    #define INPUT_FORMAT_COUNT 1
+    #define INPUT_FORMAT_COUNT 2
 #endif
 
 /**
@@ -993,7 +993,7 @@
 #endif
 
 #ifndef STREAM_FORMAT_INPUT_2_RESOLUTION_BITS
-    #define STREAM_FORMAT_INPUT_2_RESOLUTION_BITS           24
+    #define STREAM_FORMAT_INPUT_2_RESOLUTION_BITS           32
 #endif
 
 #ifndef STREAM_FORMAT_INPUT_3_RESOLUTION_BITS

lib_xua/src/core/audiohub/xua_audiohub.xc

@@ -667,6 +667,12 @@ void XUA_AudioHub(chanend ?c_aud, clock ?clk_audio_mclk, clock ?clk_audio_bclk,
 
     /* Clock master clock-block from master-clock port */
     /* Note, marked unsafe since other cores may be using this mclk port */
+
+    // 加了这里就可以播放705，但是有杂音（不加的花705没有声音）
+    // set_thread_fast_mode_on();
+    // set_port_inv(p_mclk_in); // invert sense of MCLK to improve timing for external latch  
+
+    // set_thread_fast_mode_on();
     configure_clock_src(clk_audio_mclk, p_mclk_in);
 
 

lib_xua/src/core/main.xc

@@ -370,7 +370,8 @@ void usb_audio_io(chanend ?c_aud_in,
 
         /* Audio I/O core (pars additional S/PDIF TX Core) */
         {
-            thread_speed();
+            // thread_speed();
+             set_thread_fast_mode_on();
 #if (MIXER)
 #define AUDIO_CHANNEL c_mix_out
 #else
@@ -567,7 +568,7 @@ int main()
 #else
                 /* Clock port from same clock-block as I2S */
                 /* TODO remove asm() */
-                asm("ldw %0, dp[clk_audio_mclk]":"=r"(x));
+                asm("ldw %0, dp[clk_audio_mclk]":"=r"(x)); //跟这里无关
                 asm("setclk res[%0], %1"::"r"(p_for_mclk_count), "r"(x));
 #endif
                 /* Endpoint & audio buffering cores */

lib_xua/src/core/ports/audioports.xc

@@ -66,12 +66,40 @@ void ConfigAudioPorts(
     }
 #endif
 
-    unsafe
+    // unsafe
+    // {
+    //     /* Clock bitclock clock block from master clock pin (divided) */
+    //     configure_clock_src_divide(clk_audio_bclk, (port) p_mclk_in, (divide/2));
+    //     configure_port_clock_output(p_bclk, clk_audio_bclk);
+    // }
+
+#if defined(__XS2A__) || defined(__XS3A__)
+    /* Clock bitclock clock block from master clock pin (divided) */
+    configure_clock_src_divide(clk_audio_bclk, p_mclk_in, (divide/2));
+    configure_port_clock_output(p_bclk, clk_audio_bclk);
+#else
+    /* For a divide of one (i.e. bitclock == master-clock) BClk is set to clock_output mode.
+     * In this mode it outputs an edge clock on every tick of itsassociated clock_block.
+     *
+     * For all other divides, BClk is clocked by the master clock and data
+     * will be output to p_bclk to generate the bit clock.
+     */
+    if (divide == 1) /* e.g. 176.4KHz from 11.2896 */
     {
-        /* Clock bitclock clock block from master clock pin (divided) */
+        configure_port_clock_output(p_bclk, clk_audio_mclk);
-        configure_clock_src_divide(clk_audio_bclk, (port) p_mclk_in, (divide/2));
+
-        configure_port_clock_output(p_bclk, clk_audio_bclk);
+        /* Generate bit clock block straight from mclk */
+        configure_clock_src(clk_audio_bclk, p_mclk_in);
     }
+    else
+    {
+        /* bit clock port from master clock clock-clock block */
+        configure_out_port_no_ready(p_bclk, clk_audio_mclk, 0);
+
+        /* Generate bit clock block from pin */
+        configure_clock_src(clk_audio_bclk, p_bclk);
+    }
+#endif    
 
     if(!isnull(p_lrclk))
     {
@@ -128,6 +156,8 @@ void ConfigAudioPorts(
     }
 #endif
 
+    // configure_in_port_no_ready(p_lrclk, clk_audio_bclk); // dwj+
+
     /* Start clock blocks ticking */
     start_clock(clk_audio_bclk);