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Dead code tidy only.

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This commit is contained in:
Ross Owen
2014-01-20 20:31:28 +00:00
parent 735de46f7d
commit 62008112b5
1 changed files with 0 additions and 85 deletions
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85
module_usb_audio/ports/audioports.xc
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@@ -32,17 +32,6 @@ unsigned int divide)
{
#ifndef CODEC_MASTER
#if 0
{
unsigned clockResId;
unsigned portResId;
asm("add %0, %1, %2": "=r"(clockResId):"r"(clk_audio_bclk), "r"(0));
portResId = getps(clockResId | (XS1_RES_PS_CLKSRC << 4) );
if(portResId !=1)
asm("out res[%0], %1":: "r"(portResId), "r"(0));
}
#endif
/* Note this call to stop_clock() will pause forever if the port clocking the clock-block is not low.
* deliver() should return with this being the case - however, if you are having trouble the code
* above can be enabled */
@@ -67,11 +56,6 @@ unsigned int divide)
clearbuf(p_i2s_dac[i]);
}
#endif
/* Clock master clock-block from master-clock port */
// Now done outside of function
//configure_clock_src(clk_audio_mclk, p_mclk_in);
/* For a divide of one (i.e. bitclock == master-clock) BClk is set to clock_output mode.
* In this mode it outputs an edge clock on every tick of itsassociated clock_block.
*
@@ -120,11 +104,6 @@ unsigned int divide)
/* Stop bit and master clock blocks */
stop_clock(clk_audio_bclk);
//stop_clock(clk_audio_mclk);
/* Clock master clock-block from master-clock port -
* though not directly used in I2S slave mode it is required for FB */
//configure_clock_src(clk_audio_mclk, p_mclk_in);
/* Clock bclk clock-block from bclk pin */
configure_clock_src(clk_audio_bclk, p_bclk);
@@ -144,70 +123,6 @@ unsigned int divide)
configure_in_port_no_ready(p_lrclk, clk_audio_bclk);
start_clock(clk_audio_bclk);
//start_clock(clk_audio_mclk);
#endif
}
#if 0
void ConfigAudioPorts_dsd(unsigned int divide)
{
#ifndef CODEC_MASTER
/* Output 0 on BCLK to ensure clock is low
* Required as stop_clock will only complete when the clock is low
*/
//configure_out_port_no_ready(p_dsd_clk, clk_audio_bclk, 0);
//configure_clock_src(clk_audio_mclk, p_mclk_in);
configure_out_port_no_ready(p_dsd_clk, clk_audio_mclk, 0);
p_dsd_clk <: 0;
/* Stop bit and master clock blocks and clear port buffers */
stop_clock(clk_audio_bclk);
stop_clock(clk_audio_mclk);
clearbuf(p_dsd_clk);
clearbuf(p_dsd_left);
clearbuf(p_dsd_right);
/* Clock master clock-block from master-clock port */
configure_clock_src(clk_audio_mclk, p_mclk_in);
/* For a divide of one (i.e. bitclock == master-clock) BClk is set to clock_output mode.
* In this mode it outputs an edge clock on every tick of itsassociated clock_block.
*
* For all other divides, BClk is clocked by the master clock and data
* will be output to p_bclk to generate the bit clock.
*/
if (divide == 1) /* e.g. 176.4KHz from 11.2896 */
{
configure_port_clock_output(p_dsd_clk, clk_audio_mclk);
}
else
{
/* bit clock port from master clock clock-clock block */
configure_out_port_no_ready(p_dsd_clk, clk_audio_mclk, 0);
}
/* bclk clock-blocked clocked by dsd_clk pin */
configure_clock_src(clk_audio_bclk, p_dsd_clk);
configure_out_port_no_ready(p_dsd_left, clk_audio_bclk, 0);
configure_out_port_no_ready(p_dsd_right, clk_audio_bclk, 0);
/* Start clock blocks ticking */
start_clock(clk_audio_mclk);
start_clock(clk_audio_bclk);
/* bclk initial state needs to be high */
p_dsd_clk<: 0xFFFFFFFF;
/* Pause until output completes */
sync(p_dsd_clk);
#else /* CODEC_MASTER */
#error CODEC MASTER for DSD not currently implemented
#endif
}
#endif