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More work on DSD - work in progress

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This commit is contained in:
Ross Owen
2013-06-18 15:24:36 +01:00
parent 9f65af2912
commit 7c97fbdb82
4 changed files with 46 additions and 23 deletions
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4
module_usb_audio/audio.xc
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@@ -63,7 +63,7 @@ unsigned dsdMode = 0;
/* Master clock input */ /* Master clock input */
extern port p_mclk; extern port p_mclk_in;
#ifdef SPDIF #ifdef SPDIF
extern buffered out port:32 p_spdif_tx; extern buffered out port:32 p_spdif_tx;
@@ -737,7 +737,7 @@ void audio(chanend c_mix_out, chanend ?c_dig_rx, chanend ?c_config, chanend ?c)
#endif #endif
#ifdef SPDIF #ifdef SPDIF
SpdifTransmitPortConfig(p_spdif_tx, clk_mst_spd, p_mclk); SpdifTransmitPortConfig(p_spdif_tx, clk_mst_spd, p_mclk_in);
#endif #endif
/* Initialise master clock generation */ /* Initialise master clock generation */

28
module_usb_audio/main.xc
View File

@@ -96,33 +96,34 @@ on tile[AUDIO_IO_CORE] : buffered out port:32 p_lrclk = PORT_I2S_LRCLK;
on tile[AUDIO_IO_CORE] : buffered out port:32 p_bclk = PORT_I2S_BCLK; on tile[AUDIO_IO_CORE] : buffered out port:32 p_bclk = PORT_I2S_BCLK;
#else #else
on tile[AUDIO_IO_CORE] : in port p_lrclk = PORT_I2S_LRCLK; on tile[AUDIO_IO_CORE] : in port p_lrclk = PORT_I2S_LRCLK;
on tile[AUDIO_IO_CORE] : in port p_bclk = PORT_I2S_BCLK; on tile[AUDIO_IO_CORE] : in port p_bclk = PORT_I2S_BCLK;
#endif #endif
on tile[AUDIO_IO_CORE] : port p_mclk = PORT_MCLK_IN; on tile[AUDIO_IO_CORE] : port p_mclk_in = PORT_MCLK_IN;
on tile[0] : in port p_for_mclk_count = PORT_MCLK_COUNT; on tile[0] : in port p_for_mclk_count = PORT_MCLK_COUNT;
#ifdef SPDIF #ifdef SPDIF
on tile[AUDIO_IO_CORE] : buffered out port:32 p_spdif_tx = PORT_SPDIF_OUT; on tile[AUDIO_IO_CORE] : buffered out port:32 p_spdif_tx = PORT_SPDIF_OUT;
#endif #endif
#ifdef MIDI #ifdef MIDI
on tile[AUDIO_IO_CORE] : port p_midi_tx = PORT_MIDI_OUT; on tile[AUDIO_IO_CORE] : port p_midi_tx = PORT_MIDI_OUT;
on tile[AUDIO_IO_CORE] : port p_midi_rx = PORT_MIDI_IN; on tile[AUDIO_IO_CORE] : port p_midi_rx = PORT_MIDI_IN;
#endif #endif
/* Clock blocks */ /* Clock blocks */
#ifdef MIDI #ifdef MIDI
on tile[AUDIO_IO_CORE] : clock clk_midi = XS1_CLKBLK_REF; on tile[AUDIO_IO_CORE] : clock clk_midi = XS1_CLKBLK_REF;
#endif #endif
on tile[AUDIO_IO_CORE] : clock clk_audio_mclk = XS1_CLKBLK_2; /* Master clock */ on tile[AUDIO_IO_CORE] : clock clk_audio_mclk = XS1_CLKBLK_2; /* Master clock */
#if(AUDIO_IO_CORE != 0) #if(AUDIO_IO_CORE != 0)
on tile[0] : clock clk_audio_mclk2 = XS1_CLKBLK_2; /* Master clock */ on tile[0] : clock clk_audio_mclk2 = XS1_CLKBLK_2; /* Master clock */
on tile[0] : in port p_mclk_in2 = PORT_MCLK_IN2;
#endif #endif
on tile[AUDIO_IO_CORE] : clock clk_audio_bclk = XS1_CLKBLK_3; /* Bit clock */ on tile[AUDIO_IO_CORE] : clock clk_audio_bclk = XS1_CLKBLK_3; /* Bit clock */
#ifdef SPDIF #ifdef SPDIF
on tile[AUDIO_IO_CORE] : clock clk_mst_spd = XS1_CLKBLK_1; on tile[AUDIO_IO_CORE] : clock clk_mst_spd = XS1_CLKBLK_1;
#endif #endif
@@ -246,11 +247,14 @@ int main()
{ {
unsigned x; unsigned x;
#if(AUDIO_IO_CORE != 0) #if(AUDIO_IO_CORE != 0)
asm("ldw %0, dp[clk_audio_mclk2]":"=r"(x)); set_clock_src(clk_audio_mclk2, p_mclk_in2);
set_port_clock(p_for_mclk_count, clk_audio_mclk2);
start_clock(clk_audio_mclk2);
#else #else
/* Uses same clock-block as I2S */
asm("ldw %0, dp[clk_audio_mclk]":"=r"(x)); asm("ldw %0, dp[clk_audio_mclk]":"=r"(x));
#endif
asm("setclk res[%0], %1"::"r"(p_for_mclk_count), "r"(x)); asm("setclk res[%0], %1"::"r"(p_for_mclk_count), "r"(x));
#endif
} }
buffer(c_xud_out[EP_NUM_OUT_AUD],/* Audio Out*/ buffer(c_xud_out[EP_NUM_OUT_AUD],/* Audio Out*/

3
module_usb_audio/ports/audioports.c
View File

@@ -1,5 +1,6 @@
#include <xccompat.h> #include <xccompat.h>
#include "devicedefines.h"
#include "audioports.h" #include "audioports.h"
//#define p_dsd_left p_i2s_dac[0] //#define p_dsd_left p_i2s_dac[0]
@@ -28,6 +29,8 @@ dsdPorts[0] = PORT_DSD_DAC0;
#endif #endif
/* C wrapper for ConfigAudioPorts() such that we can mess around with arrays of ports */
void ConfigAudioPortsWrapper( void ConfigAudioPortsWrapper(
#if (I2S_CHANS_DAC != 0) #if (I2S_CHANS_DAC != 0)
port p_i2s_dac[I2S_WIRES_DAC], port p_i2s_dac[I2S_WIRES_DAC],

34
module_usb_audio/ports/audioports.xc
View File

@@ -3,13 +3,29 @@
#include "devicedefines.h" #include "devicedefines.h"
#include "audioports.h" #include "audioports.h"
/* Configure audio ports. This is in C such that can we can mess around with arrays of ports */ #ifdef DSD_OUTPUT
#error Building audioports with DSD
#ifndef p_dsd_clk
buffered out port:32 p_dsd_clk = P_DSD_CLK;
#endif
//extern void configure_in_port_no_ready(port p, const clock clk); #ifndef p_dsd_left
//extern void configure_out_port_no_ready(port p, const clock clk, unsigned initial); extern buffered out port:32 p_dsd_left;
//extern void configure_clock_src(clock clk, port p); #endif
extern port p_mclk; #ifndef p_dsd_right
extern buffered out port:32 p_dsd_right;
#endif
#if I2S_WIRES_DAC > 0
#ifndef p_dsd_dac0
on tile[0] : buffered out port:32 p_dsd_dac0 = PORT_DSD_DAC0;
#endif
dsdPorts[0] = PORT_DSD_DAC0;
#endif
#endif
extern port p_mclk_in;
extern clock clk_audio_mclk; extern clock clk_audio_mclk;
extern clock clk_audio_bclk; extern clock clk_audio_bclk;
@@ -68,7 +84,7 @@ unsigned int divide)
#endif #endif
/* Clock master clock-block from master-clock port */ /* Clock master clock-block from master-clock port */
configure_clock_src(clk_audio_mclk, p_mclk); configure_clock_src(clk_audio_mclk, p_mclk_in);
/* For a divide of one (i.e. bitclock == master-clock) BClk is set to clock_output mode. /* For a divide of one (i.e. bitclock == master-clock) BClk is set to clock_output mode.
* In this mode it outputs an edge clock on every tick of itsassociated clock_block. * In this mode it outputs an edge clock on every tick of itsassociated clock_block.
@@ -127,7 +143,7 @@ unsigned int divide)
/* Clock master clock-block from master-clock port - /* Clock master clock-block from master-clock port -
* though not directly used in I2S slave mode it is required for FB */ * though not directly used in I2S slave mode it is required for FB */
configure_clock_src(clk_audio_mclk, p_mclk); configure_clock_src(clk_audio_mclk, p_mclk_in);
/* Clock bclk clock-block from bclk pin */ /* Clock bclk clock-block from bclk pin */
configure_clock_src(clk_audio_bclk, p_bclk); configure_clock_src(clk_audio_bclk, p_bclk);
@@ -161,7 +177,7 @@ void ConfigAudioPorts_dsd(unsigned int divide)
* Required as stop_clock will only complete when the clock is low * Required as stop_clock will only complete when the clock is low
*/ */
//configure_out_port_no_ready(p_dsd_clk, clk_audio_bclk, 0); //configure_out_port_no_ready(p_dsd_clk, clk_audio_bclk, 0);
//configure_clock_src(clk_audio_mclk, p_mclk); //configure_clock_src(clk_audio_mclk, p_mclk_in);
configure_out_port_no_ready(p_dsd_clk, clk_audio_mclk, 0); configure_out_port_no_ready(p_dsd_clk, clk_audio_mclk, 0);
p_dsd_clk <: 0; p_dsd_clk <: 0;
@@ -174,7 +190,7 @@ void ConfigAudioPorts_dsd(unsigned int divide)
clearbuf(p_dsd_right); clearbuf(p_dsd_right);
/* Clock master clock-block from master-clock port */ /* Clock master clock-block from master-clock port */
configure_clock_src(clk_audio_mclk, p_mclk); configure_clock_src(clk_audio_mclk, p_mclk_in);
/* For a divide of one (i.e. bitclock == master-clock) BClk is set to clock_output mode. /* For a divide of one (i.e. bitclock == master-clock) BClk is set to clock_output mode.
* In this mode it outputs an edge clock on every tick of itsassociated clock_block. * In this mode it outputs an edge clock on every tick of itsassociated clock_block.