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fix adat and spdif rx enable defines used in the test to match those used in the test makefile

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This commit is contained in:
Shuchita Khare
2024-05-10 14:02:11 +01:00
parent ad91d19f94
commit 7ea3ead62d
2 changed files with 6 additions and 6 deletions
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2
lib_xua/api/xua_conf_default.h
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@@ -1255,7 +1255,7 @@
#endif #endif
#if (XUA_SYNCMODE == XUA_SYNCMODE_SYNC) #if (XUA_SYNCMODE == XUA_SYNCMODE_SYNC)
#if (XUA_SPDIF_RX_EN|| ADAT_RX) #if (XUA_SPDIF_RX_EN|| XUA_ADAT_RX_EN)
#error "Digital input streams not supported in Sync mode" #error "Digital input streams not supported in Sync mode"
#endif #endif
#endif #endif

10
tests/test_i2s_loopback/xk_216_mc/audiohw.xc
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@@ -1,4 +1,4 @@
// Copyright 2016-2022 XMOS LIMITED. // Copyright 2016-2024 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1. // This Software is subject to the terms of the XMOS Public Licence: Version 1.
#ifdef HARDWARE #ifdef HARDWARE
@@ -19,7 +19,7 @@
/* CS2100 lists typical lock time as 100 * input period */ /* CS2100 lists typical lock time as 100 * input period */
#define AUDIO_PLL_LOCK_DELAY (40000000) #define AUDIO_PLL_LOCK_DELAY (40000000)
#if defined(SPDIF_RX) || defined(ADAT_RX) #if defined(XUA_SPDIF_RX_EN) || defined(XUA_ADAT_RX_EN)
#define USE_FRACTIONAL_N 1 #define USE_FRACTIONAL_N 1
#endif #endif
@@ -32,7 +32,7 @@ port p_i2c = on tile[0]:PORT_I2C;
#ifdef USE_FRACTIONAL_N #ifdef USE_FRACTIONAL_N
#if !(defined(SPDIF_RX) || defined(ADAT_RX)) #if !(defined(XUA_SPDIF_RX_EN) || defined(XUA_ADAT_RX_EN))
/* Choose a frequency the xcore can easily generate internally */ /* Choose a frequency the xcore can easily generate internally */
#define PLL_SYNC_FREQ 1000000 #define PLL_SYNC_FREQ 1000000
#else #else
@@ -95,7 +95,7 @@ void PllMult(unsigned output, unsigned ref, client interface i2c_master_if i2c)
} }
#endif #endif
#if !(defined(SPDIF_RX) || defined(ADAT_RX)) && defined(USE_FRACTIONAL_N) #if !(defined(XUA_SPDIF_RX_EN) || defined(XUA_ADAT_RX_EN)) && defined(USE_FRACTIONAL_N)
on tile[AUDIO_IO_TILE] : out port p_pll_clk = PORT_PLL_REF; on tile[AUDIO_IO_TILE] : out port p_pll_clk = PORT_PLL_REF;
on tile[AUDIO_IO_TILE] : clock clk_pll_sync = XS1_CLKBLK_5; on tile[AUDIO_IO_TILE] : clock clk_pll_sync = XS1_CLKBLK_5;
#endif #endif
@@ -111,7 +111,7 @@ void wait_us(int microseconds)
void AudioHwInit(chanend ?c_codec) void AudioHwInit(chanend ?c_codec)
{ {
#if !(defined(SPDIF_RX) || defined(ADAT_RX)) && defined(USE_FRACTIONAL_N) #if !(defined(XUA_SPDIF_RX_EN) || defined(XUA_ADAT_RX_EN)) && defined(USE_FRACTIONAL_N)
/* Output a fixed sync clock to the pll */ /* Output a fixed sync clock to the pll */
configure_clock_rate(clk_pll_sync, 100, 100/(PLL_SYNC_FREQ/1000000)); configure_clock_rate(clk_pll_sync, 100, 100/(PLL_SYNC_FREQ/1000000));
configure_port_clock_output(p_pll_clk, clk_pll_sync); configure_port_clock_output(p_pll_clk, clk_pll_sync);