From 855ba6b83f6165a60f750c9ccb8ba54b0e9aa74d Mon Sep 17 00:00:00 2001 From: Ross Owen Date: Thu, 19 Dec 2013 11:55:34 +0000 Subject: [PATCH] Fixed up null USB reset port but not null USB clock. This is for case when UserReset is used to reset USB phy (L1 iOS board has USB phy rst on shiftreg --- module_usb_audio/main.xc | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/module_usb_audio/main.xc b/module_usb_audio/main.xc index 036a4cca..93966acb 100755 --- a/module_usb_audio/main.xc +++ b/module_usb_audio/main.xc @@ -138,16 +138,18 @@ on tile[AUDIO_IO_TILE] : clock clk_mst_spd = XS1_CLKBLK_1; #endif /* L Series needs a port to use for USB reset */ -#if defined(ARCH_L) || defined(ARCH_G) -#ifdef PORT_USB_RESET +#if (defined(ARCH_L) || defined(ARCH_G)) && defined(PORT_USB_RESET) /* This define is checked since it could be on a shift reg or similar */ on tile[XUD_TILE] : out port p_usb_rst = PORT_USB_RESET; +#else +/* Reset port not required for U series due to built in Phy */ +#define p_usb_rst null #endif + +#if defined (ARCH_L) || defined(ARCH_G) /* L Series also needs a clock for this port */ on tile[XUD_TILE] : clock clk = XS1_CLKBLK_4; #else -/* Reset port not required for SU1 due to built in Phy */ -#define p_usb_rst null #define clk null #endif