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Tidy defines

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Ed
2024-01-09 09:10:14 +00:00
parent 3003ce7241
commit 87a105d8f6
2 changed files with 9 additions and 6 deletions
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8
lib_xua/src/core/clocking/sw_pll_wrapper.h
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@@ -1,6 +1,9 @@
// Copyright 2024 XMOS LIMITED. // Copyright 2024 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1. // This Software is subject to the terms of the XMOS Public Licence: Version 1.
#ifndef _SW_PLL_WRAPPPER_H_
#define _SW_PLL_WRAPPPER_H_
/* By default we use SW_PLL for Digital Rx configs running on XCORE-AI */ /* By default we use SW_PLL for Digital Rx configs running on XCORE-AI */
/* Note: Not yet implemented for Synchronous mode */ /* Note: Not yet implemented for Synchronous mode */
#ifdef __XS3A__ #ifdef __XS3A__
@@ -11,7 +14,7 @@
#define USE_SW_PLL 0 #define USE_SW_PLL 0
#endif /* __XS3A__ */ #endif /* __XS3A__ */
#if USE_SW_PLL
extern "C" extern "C"
{ {
#include "sw_pll.h" #include "sw_pll.h"
@@ -56,3 +59,6 @@ void do_sw_pll_phase_frequency_detector_dig_rx( unsigned short mclk_time_stamp,
* \param mClk The current nominal mClk frequency. * \param mClk The current nominal mClk frequency.
*/ */
unsigned InitSWPLL(sw_pll_state_t &sw_pll, unsigned mClk); unsigned InitSWPLL(sw_pll_state_t &sw_pll, unsigned mClk);
#endif /* USE_SW_PLL */
#endif /* _SW_PLL_WRAPPPER_H_ */

7
lib_xua/src/core/clocking/sw_pll_wrapper.xc
View File

@@ -5,12 +5,9 @@
#include <print.h> #include <print.h>
#include "sw_pll_wrapper.h" #include "sw_pll_wrapper.h"
#include "xua.h"
#if USE_SW_PLL #if USE_SW_PLL
extern "C"
{
#include "sw_pll.h"
}
/* Pointer to sw_pll struct to allow it to be used in separate SDM thread */ /* Pointer to sw_pll struct to allow it to be used in separate SDM thread */
unsafe unsafe
@@ -212,4 +209,4 @@ void disable_sigma_delta(chanend c_sigma_delta)
inuint(c_sigma_delta); /* Wait for ACK so we know reg write is complete */ inuint(c_sigma_delta); /* Wait for ACK so we know reg write is complete */
} }
#endif #endif /* USE_SW_PLL */