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Fixed I2S data offset when xCORE-200 H/W bit clock-divide used (startup code change)

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This commit is contained in:
Ross Owen
2015-11-17 17:47:00 +00:00
parent 2130da665e
commit 8fdc9b0986
2 changed files with 28 additions and 27 deletions
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12
module_usb_audio/audio.xc
View File

@@ -109,8 +109,7 @@ extern void device_reboot(void);
#ifndef CODEC_MASTER #ifndef CODEC_MASTER
static inline void doI2SClocks(unsigned divide) static inline void doI2SClocks(unsigned divide)
{ {
//#ifndef __XS2A__ #ifndef __XS2A__
#if 1
switch (divide) switch (divide)
{ {
#if (MAX_DIVIDE > 16) #if (MAX_DIVIDE > 16)
@@ -304,12 +303,14 @@ static inline void InitPorts(unsigned divide)
{ {
#endif #endif
#if !defined(__XS2A__)
if(divide != 1) if(divide != 1)
{ {
/* b_clk must start high */ /* b_clk must start high */
p_bclk <: 0x80000000; p_bclk <: 0x80000000;
sync(p_bclk); sync(p_bclk);
} }
#endif
/* Clear I2S port buffers */ /* Clear I2S port buffers */
clearbuf(p_lrclk); clearbuf(p_lrclk);
@@ -327,7 +328,12 @@ static inline void InitPorts(unsigned divide)
clearbuf(p_i2s_adc[i]); clearbuf(p_i2s_adc[i]);
} }
#endif #endif
#if defined(__XS2A__)
if(1)
#else
if(divide == 1) if(divide == 1)
#endif
{ {
#pragma xta endpoint "divide_1" #pragma xta endpoint "divide_1"
p_lrclk <: 0 @ tmp; p_lrclk <: 0 @ tmp;
@@ -353,8 +359,6 @@ static inline void InitPorts(unsigned divide)
} }
else /* Divide != 1 */ else /* Divide != 1 */
{ {
#if (I2S_CHANS_DAC != 0) #if (I2S_CHANS_DAC != 0)
/* Pre-fill the DAC ports */ /* Pre-fill the DAC ports */
for(int i = 0; i < I2S_WIRES_DAC; i++) for(int i = 0; i < I2S_WIRES_DAC; i++)

17
module_usb_audio/ports/audioports.xc
View File

@@ -30,8 +30,6 @@ void ConfigAudioPorts(
#endif #endif
unsigned int divide) unsigned int divide)
{ {
printintln(divide);
#if !defined(CODEC_MASTER) #if !defined(CODEC_MASTER)
/* Note this call to stop_clock() will pause forever if the port clocking the clock-block is not low. /* Note this call to stop_clock() will pause forever if the port clocking the clock-block is not low.
* deliver() should return with this being the case */ * deliver() should return with this being the case */
@@ -56,6 +54,12 @@ unsigned int divide)
clearbuf(p_i2s_dac[i]); clearbuf(p_i2s_dac[i]);
} }
#endif #endif
#if defined(__XS2A__)
/* Clock bitclock clock block from master clock pin (divided) */
configure_clock_src_divide(clk_audio_bclk, p_mclk_in, (divide/2));
configure_port_clock_output(p_bclk, clk_audio_bclk);
#else
/* For a divide of one (i.e. bitclock == master-clock) BClk is set to clock_output mode. /* For a divide of one (i.e. bitclock == master-clock) BClk is set to clock_output mode.
* In this mode it outputs an edge clock on every tick of itsassociated clock_block. * In this mode it outputs an edge clock on every tick of itsassociated clock_block.
* *
@@ -71,20 +75,13 @@ unsigned int divide)
} }
else else
{ {
//#if defined(__XS2A__)
#if 0
/* Clock bitclock clock block from master clock pin (divided) */
configure_clock_src_divide(clk_audio_bclk, p_mclk_in, divide / 2);
configure_port_clock_output(p_bclk, clk_audio_bclk);
#else
/* bit clock port from master clock clock-clock block */ /* bit clock port from master clock clock-clock block */
configure_out_port_no_ready(p_bclk, clk_audio_mclk, 0); configure_out_port_no_ready(p_bclk, clk_audio_mclk, 0);
/* Generate bit clock block from pin */ /* Generate bit clock block from pin */
configure_clock_src(clk_audio_bclk, p_bclk); configure_clock_src(clk_audio_bclk, p_bclk);
#endif
} }
#endif
if(!isnull(p_lrclk)) if(!isnull(p_lrclk))
{ {