From a4e6fd0194aa4240b6dbedafcad7b204f1c3639f Mon Sep 17 00:00:00 2001 From: Ed Date: Mon, 15 Jan 2024 10:39:09 +0000 Subject: [PATCH] More tidying --- lib_xua/src/core/clocking/clockgen.xc | 7 ++++--- lib_xua/src/core/clocking/sw_pll_wrapper.h | 2 +- lib_xua/src/core/clocking/sw_pll_wrapper.xc | 4 ++-- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/lib_xua/src/core/clocking/clockgen.xc b/lib_xua/src/core/clocking/clockgen.xc index a8164a1e..08040504 100644 --- a/lib_xua/src/core/clocking/clockgen.xc +++ b/lib_xua/src/core/clocking/clockgen.xc @@ -107,7 +107,6 @@ static inline void setClockValidity(chanend c_interruptControl, int clkIndex, in { clockValid[clkIndex] = valid; outInterrupt(c_interruptControl, clockId[clkIndex]); - printstr("clockValid=");printintln(valid); #ifdef CLOCK_VALIDITY_CALL #if (XUA_ADAT_RX_EN) @@ -349,6 +348,7 @@ void clockGen ( streaming chanend ?c_spdif_rx, int reset_sw_pll_pfd = 1; int require_ack_to_audio = 0; + /* Set selected_mclk_rate_ptr to point at local var selected_mclk_rate */ unsafe { selected_mclk_rate_ptr = &selected_mclk_rate; } @@ -535,7 +535,8 @@ void clockGen ( streaming chanend ?c_spdif_rx, #if ((XUA_SPDIF_RX_EN || XUA_ADAT_RX_EN) && USE_SW_PLL) case inuint_byref(c_sigma_delta, tmp): - /* Send ACK back to audiohub to allow I2S to start */ + /* Send ACK back to audiohub to allow I2S to start + This happens only on SDM restart and only once */ if(require_ack_to_audio) { c_mclk_change <: tmp; @@ -545,7 +546,7 @@ void clockGen ( streaming chanend ?c_spdif_rx, #endif #if (XUA_SPDIF_RX_EN || XUA_ADAT_RX_EN) - /* Receive notification of audio streaming settings change */ + /* Receive notification of audio streaming settings change and store */ case c_mclk_change :> selected_mclk_rate: c_mclk_change :> selected_sample_rate; #if USE_SW_PLL diff --git a/lib_xua/src/core/clocking/sw_pll_wrapper.h b/lib_xua/src/core/clocking/sw_pll_wrapper.h index bc96c1ea..be808696 100644 --- a/lib_xua/src/core/clocking/sw_pll_wrapper.h +++ b/lib_xua/src/core/clocking/sw_pll_wrapper.h @@ -58,7 +58,7 @@ void do_sw_pll_phase_frequency_detector_dig_rx( unsigned short mclk_time_stamp, * \param sw_pll Reference to a software pll state struct to be initialised. * \param mClk The current nominal mClk frequency. * - * returns The SDM update interval and the initial DCO setting for nominal frequency */ + * returns The SDM update interval in ticks and the initial DCO setting for nominal frequency */ {unsigned, unsigned} InitSWPLL(sw_pll_state_t &sw_pll, unsigned mClk); #endif /* USE_SW_PLL */ diff --git a/lib_xua/src/core/clocking/sw_pll_wrapper.xc b/lib_xua/src/core/clocking/sw_pll_wrapper.xc index 95c67057..7cb3163d 100644 --- a/lib_xua/src/core/clocking/sw_pll_wrapper.xc +++ b/lib_xua/src/core/clocking/sw_pll_wrapper.xc @@ -126,7 +126,7 @@ void SigmaDeltaTask(chanend c_sigma_delta, unsigned * unsafe selected_mclk_rate_ unsafe { - printf("SigmaDeltaTask: %u\n", *selected_mclk_rate_ptr); + /* initialse the SDM and gather SDM initial settings */ {sdm_interval, dco_setting} = InitSWPLL(sw_pll, (unsigned)*selected_mclk_rate_ptr); } @@ -162,7 +162,7 @@ void SigmaDeltaTask(chanend c_sigma_delta, unsigned * unsafe selected_mclk_rate_ } break; - // Do nothing & fall-through + /* Do nothing & fall-through. Above case polls only once per loop */ default: break; }