WIP Adaptive with PLL nudge (demo working)

examples/xua_lite_example/src/pdm_mic.xc

@@ -74,4 +74,36 @@ void pdm_mic(streaming chanend c_ds_output, in buffered port:32 p_pdm_mics)
 
     }
 }
+
+void mic_array_setup_ddr_xcore(clock pdmclk,
+                         clock pdmclk6,
+                         out port p_pdm_clk,
+                         buffered in port:32 p_pdm_data,
+                         int divide) {
+    configure_clock_xcore(pdmclk, 80);
+    //configure_clock_src_divide(pdmclk, p_mclk, divide/2);
+
+    configure_clock_xcore(pdmclk6, 40);
+    //configure_clock_src_divide(pdmclk6, p_mclk, divide/4);
+    
+    configure_port_clock_output(p_pdm_clk, pdmclk);
+    configure_in_port(p_pdm_data, pdmclk6);
+
+    /* start the faster capture clock */
+    start_clock(pdmclk6);
+    /* wait for a rising edge on the capture clock */
+    partin(p_pdm_data, 4);
+    /* start the slower output clock */
+    start_clock(pdmclk);
+
+    /*
+     * this results in the rising edge of the capture clock
+     * leading the rising edge of the output clock by one period
+     * of p_mclk, which is about 40.7 ns for the typical frequency
+     * of 24.576 megahertz.
+     * This should fall within the data valid window.
+     */
+
+}
+
 #endif