forked from PAWPAW-Mirror/lib_xua
Merge commit 'cb690527c9907dda021101f2bcfa28fa5a3f844a' into fetaure/multi_interface
# Conflicts: # CHANGELOG.rst
This commit is contained in:
@@ -13,6 +13,9 @@ UNRELEASED
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* FIXED: ADAT Tx called too frequently
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* FIXED: ADAT Tx called too frequently
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* CHANGED: ADAT Tx presents different channel count interfaces based on sample
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* CHANGED: ADAT Tx presents different channel count interfaces based on sample
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rate
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rate
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* CHANGED: aud_to_host buffer size and the condition to come out of underflow
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in decoupler to fix buffer underflow seen in ADAT tests
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* FIXED: Initialise SMUX based on DEFAULT_FREQ in clockgen
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4.0.0
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4.0.0
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-----
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-----
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@@ -1318,7 +1318,7 @@
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#endif
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#endif
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#if (XUA_SYNCMODE == XUA_SYNCMODE_SYNC)
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#if (XUA_SYNCMODE == XUA_SYNCMODE_SYNC)
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#if (XUA_SPDIF_RX_EN|| ADAT_RX)
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#if (XUA_SPDIF_RX_EN|| XUA_ADAT_RX_EN)
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#error "Digital input streams not supported in Sync mode"
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#error "Digital input streams not supported in Sync mode"
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#endif
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#endif
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#endif
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#endif
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@@ -1,4 +1,4 @@
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// Copyright 2011-2023 XMOS LIMITED.
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// Copyright 2011-2024 XMOS LIMITED.
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// This Software is subject to the terms of the XMOS Public Licence: Version 1.
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// This Software is subject to the terms of the XMOS Public Licence: Version 1.
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#include "xua.h"
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#include "xua.h"
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@@ -42,8 +42,13 @@
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#define MAX_DEVICE_AUD_PACKET_SIZE_OUT (MAX(MAX_DEVICE_AUD_PACKET_SIZE_OUT_FS, MAX_DEVICE_AUD_PACKET_SIZE_OUT_HS))
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#define MAX_DEVICE_AUD_PACKET_SIZE_OUT (MAX(MAX_DEVICE_AUD_PACKET_SIZE_OUT_FS, MAX_DEVICE_AUD_PACKET_SIZE_OUT_HS))
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/*** BUFFER SIZES ***/
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/*** BUFFER SIZES ***/
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/* How many packets too allow for in buffer - minimum is 5.
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#define BUFFER_PACKET_COUNT (4) /* How many packets too allow for in buffer - minimum is 4 */
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2 for having in the aud_to_host buffer when it comes out of underflow, space available for 2 more for to accomodate cases when
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2 pkts from audio hub get written into the aud_to_host buffer within 1 SOF period, and space for 1 extra packet to ensure that
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when the 4th packet gets written to the buffer, there's space to accomodate the next packet, otherwise handle_audio_request() will
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drop packets after writing the 4th packet in the buffer
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*/
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#define BUFFER_PACKET_COUNT (5)
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#define BUFF_SIZE_OUT_HS MAX_DEVICE_AUD_PACKET_SIZE_OUT_HS * BUFFER_PACKET_COUNT
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#define BUFF_SIZE_OUT_HS MAX_DEVICE_AUD_PACKET_SIZE_OUT_HS * BUFFER_PACKET_COUNT
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#define BUFF_SIZE_OUT_FS MAX_DEVICE_AUD_PACKET_SIZE_OUT_FS * BUFFER_PACKET_COUNT
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#define BUFF_SIZE_OUT_FS MAX_DEVICE_AUD_PACKET_SIZE_OUT_FS * BUFFER_PACKET_COUNT
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@@ -1054,7 +1059,21 @@ void XUA_Buffer_Decouple(chanend c_mix_out
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assert(fillLevel <= BUFF_SIZE_IN);
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assert(fillLevel <= BUFF_SIZE_IN);
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/* Check if we have come out of underflow */
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/* Check if we have come out of underflow */
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if (fillLevel >= IN_BUFFER_PREFILL)
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unsigned sampFreq;
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GET_SHARED_GLOBAL(sampFreq, g_freqChange_sampFreq);
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int min, mid, max;
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GetADCCounts(sampFreq, min, mid, max);
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const int min_pkt_size = ((min * g_curSubSlot_In * g_numUsbChan_In + 3) & ~0x3) + 4;
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/*
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Come out of underflow if there are exactly 2 packets in the buffer.
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This ensures that handle_audio_request() does not drop packets when writing packets into the aud_to_host buffer
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when aud_to_host buffer is not in underflow.
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For example, coming out of underflow with 3 packets in the buffer would mean handle_audio_request()
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drops packets if 2 pkts are received from audio hub in 1 SOF period. Coming out of underflow with 4
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packets would mean handle_audio_request would drop packets after writing 1 packet to the aud_to_host buffer.
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*/
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if ((fillLevel >= (min_pkt_size*2)) && (fillLevel < (min_pkt_size*3)))
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{
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{
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int aud_to_host_rdptr;
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int aud_to_host_rdptr;
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GET_SHARED_GLOBAL(aud_to_host_rdptr, g_aud_to_host_rdptr);
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GET_SHARED_GLOBAL(aud_to_host_rdptr, g_aud_to_host_rdptr);
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@@ -235,7 +235,23 @@ void clockGen ( streaming chanend ?c_spdif_rx,
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unsigned tmp;
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unsigned tmp;
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/* Start in no-SMUX (8-channel) mode */
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/* Start in no-SMUX (8-channel) mode */
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int smux = 0;
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int smux;
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// Initialise smux based based on the DEFAULT_FREQ
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if(DEFAULT_FREQ < 88200)
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{
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/* No SMUX */
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smux = 0;
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}
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else if(DEFAULT_FREQ < 176400)
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{
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/* SMUX */
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smux = 1;
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}
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else
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{
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/* SMUX II */
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smux = 2;
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}
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#ifdef LEVEL_METER_LEDS
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#ifdef LEVEL_METER_LEDS
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timer t_level;
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timer t_level;
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@@ -1,4 +1,4 @@
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// Copyright 2016-2022 XMOS LIMITED.
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// Copyright 2016-2024 XMOS LIMITED.
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// This Software is subject to the terms of the XMOS Public Licence: Version 1.
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// This Software is subject to the terms of the XMOS Public Licence: Version 1.
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#ifdef HARDWARE
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#ifdef HARDWARE
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@@ -19,7 +19,7 @@
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/* CS2100 lists typical lock time as 100 * input period */
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/* CS2100 lists typical lock time as 100 * input period */
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#define AUDIO_PLL_LOCK_DELAY (40000000)
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#define AUDIO_PLL_LOCK_DELAY (40000000)
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#if defined(SPDIF_RX) || defined(ADAT_RX)
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#if defined(XUA_SPDIF_RX_EN) || defined(XUA_ADAT_RX_EN)
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#define USE_FRACTIONAL_N 1
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#define USE_FRACTIONAL_N 1
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#endif
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#endif
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@@ -32,7 +32,7 @@ port p_i2c = on tile[0]:PORT_I2C;
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#ifdef USE_FRACTIONAL_N
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#ifdef USE_FRACTIONAL_N
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#if !(defined(SPDIF_RX) || defined(ADAT_RX))
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#if !(defined(XUA_SPDIF_RX_EN) || defined(XUA_ADAT_RX_EN))
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/* Choose a frequency the xcore can easily generate internally */
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/* Choose a frequency the xcore can easily generate internally */
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#define PLL_SYNC_FREQ 1000000
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#define PLL_SYNC_FREQ 1000000
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#else
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#else
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@@ -95,7 +95,7 @@ void PllMult(unsigned output, unsigned ref, client interface i2c_master_if i2c)
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}
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}
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#endif
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#endif
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#if !(defined(SPDIF_RX) || defined(ADAT_RX)) && defined(USE_FRACTIONAL_N)
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#if !(defined(XUA_SPDIF_RX_EN) || defined(XUA_ADAT_RX_EN)) && defined(USE_FRACTIONAL_N)
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on tile[AUDIO_IO_TILE] : out port p_pll_clk = PORT_PLL_REF;
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on tile[AUDIO_IO_TILE] : out port p_pll_clk = PORT_PLL_REF;
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on tile[AUDIO_IO_TILE] : clock clk_pll_sync = XS1_CLKBLK_5;
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on tile[AUDIO_IO_TILE] : clock clk_pll_sync = XS1_CLKBLK_5;
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#endif
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#endif
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@@ -111,7 +111,7 @@ void wait_us(int microseconds)
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void AudioHwInit(chanend ?c_codec)
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void AudioHwInit(chanend ?c_codec)
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{
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{
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#if !(defined(SPDIF_RX) || defined(ADAT_RX)) && defined(USE_FRACTIONAL_N)
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#if !(defined(XUA_SPDIF_RX_EN) || defined(XUA_ADAT_RX_EN)) && defined(USE_FRACTIONAL_N)
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/* Output a fixed sync clock to the pll */
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/* Output a fixed sync clock to the pll */
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configure_clock_rate(clk_pll_sync, 100, 100/(PLL_SYNC_FREQ/1000000));
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configure_clock_rate(clk_pll_sync, 100, 100/(PLL_SYNC_FREQ/1000000));
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configure_port_clock_output(p_pll_clk, clk_pll_sync);
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configure_port_clock_output(p_pll_clk, clk_pll_sync);
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