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Added use of XUD_TILE def

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Ross Owen
2013-11-29 12:33:41 +00:00
parent 98d08e18c5
commit edca022c50
1 changed files with 12 additions and 8 deletions
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20
module_usb_audio/main.xc
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@@ -3,7 +3,6 @@
* @brief Top level for XMOS USB 2.0 Audio 2.0 Reference Designs. * @brief Top level for XMOS USB 2.0 Audio 2.0 Reference Designs.
* @author Ross Owen, XMOS Semiconductor Ltd * @author Ross Owen, XMOS Semiconductor Ltd
*/ */
#include <syscall.h> #include <syscall.h>
#include <platform.h> #include <platform.h>
#include <xs1.h> #include <xs1.h>
@@ -30,10 +29,14 @@
#endif #endif
#ifndef AUDIO_IO_TILE #ifndef AUDIO_IO_TILE
#define AUDIO_IO_TILE 0 #define AUDIO_IO_TILE 0
#endif #endif
/* Audio I/O */ #ifndef XUD_TILE
#define XUD_TILE 0
#endif
/* Audio I/O - Port declarations */
#if I2S_WIRES_DAC > 0 #if I2S_WIRES_DAC > 0
on tile[AUDIO_IO_TILE] : buffered out port:32 p_i2s_dac[I2S_WIRES_DAC] = on tile[AUDIO_IO_TILE] : buffered out port:32 p_i2s_dac[I2S_WIRES_DAC] =
{PORT_I2S_DAC0, {PORT_I2S_DAC0,
@@ -97,7 +100,7 @@ on tile[AUDIO_IO_TILE] : buffered in port:32 p_i2s_adc[I2S_WIRES_ADC] =
on tile[AUDIO_IO_TILE] : buffered out port:32 p_lrclk = PORT_I2S_LRCLK; on tile[AUDIO_IO_TILE] : buffered out port:32 p_lrclk = PORT_I2S_LRCLK;
on tile[AUDIO_IO_TILE] : buffered out port:32 p_bclk = PORT_I2S_BCLK; on tile[AUDIO_IO_TILE] : buffered out port:32 p_bclk = PORT_I2S_BCLK;
#else #else
on tile[AUDIO_IO_TILE] : in port p_lrclk = PORT_I2S_LRCLK; on tile[AUDIO_IO_TILE] : in port p_lrclk = PORT_I2S_LRCLK;
on tile[AUDIO_IO_TILE] : in port p_bclk = PORT_I2S_BCLK; on tile[AUDIO_IO_TILE] : in port p_bclk = PORT_I2S_BCLK;
#endif #endif
@@ -134,10 +137,10 @@ on tile[AUDIO_IO_TILE] : clock clk_mst_spd = XS1_CLKBLK_1;
#ifdef ARCH_L #ifdef ARCH_L
#ifdef PORT_USB_RESET #ifdef PORT_USB_RESET
/* This define is checked since it could be on a shift reg or similar */ /* This define is checked since it could be on a shift reg or similar */
on tile[0] : out port p_usb_rst = PORT_USB_RESET; on tile[XUD_TILE] : out port p_usb_rst = PORT_USB_RESET;
#endif #endif
/* L Series also needs a clock for this port */ /* L Series also needs a clock for this port */
on tile[0] : clock clk = XS1_CLKBLK_4; on tile[XUD_TILE] : clock clk = XS1_CLKBLK_4;
#else #else
/* Reset port not required for SU1 due to built in Phy */ /* Reset port not required for SU1 due to built in Phy */
#define p_usb_rst null #define p_usb_rst null
@@ -145,10 +148,11 @@ on tile[0] : clock clk = XS1_CLKBLK_4;
#endif #endif
#ifdef IAP #ifdef IAP
on tile [AUDIO_IO_TILE] : port p_i2c_sda = PORT_I2C_SDA; on tile [AUDIO_IO_TILE] : port p_i2c_sda = PORT_I2C_SDA;
on tile [AUDIO_IO_TILE] : port p_i2c_scl = PORT_I2C_SCL; on tile [AUDIO_IO_TILE] : port p_i2c_scl = PORT_I2C_SCL;
#endif #endif
/* Endpoint type tables for XUD */ /* Endpoint type tables for XUD */
XUD_EpType epTypeTableOut[EP_CNT_OUT] = { XUD_EPTYPE_CTL | XUD_STATUS_ENABLE, XUD_EpType epTypeTableOut[EP_CNT_OUT] = { XUD_EPTYPE_CTL | XUD_STATUS_ENABLE,
XUD_EPTYPE_ISO, /* Audio */ XUD_EPTYPE_ISO, /* Audio */