forked from PAWPAW-Mirror/lib_xua
217 lines
6.0 KiB
Plaintext
217 lines
6.0 KiB
Plaintext
#include <xs1.h>
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#include <xccompat.h>
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#include "devicedefines.h"
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#include "audioports.h"
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/* Configure audio ports. This is in C such that can we can mess around with arrays of ports */
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//extern void configure_in_port_no_ready(port p, const clock clk);
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//extern void configure_out_port_no_ready(port p, const clock clk, unsigned initial);
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//extern void configure_clock_src(clock clk, port p);
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extern port p_mclk;
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extern clock clk_audio_mclk;
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extern clock clk_audio_bclk;
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void ConfigAudioPorts(
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#if (I2S_CHANS_DAC != 0)
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buffered out port:32 p_i2s_dac[I2S_WIRES_DAC],
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// port p_i2s_dac[I2S_WIRES_DAC],
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#endif
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#if (I2S_CHANS_ADC != 0)
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buffered in port:32 p_i2s_adc[I2S_WIRES_ADC],
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// port p_i2s_adc[I2S_WIRES_ADC],
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#endif
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#if (I2S_CHANS_DAC != 0) || (I2S_CHANS_ADC != 0)
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#ifndef CODEC_MASTER
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buffered out port:32 p_lrclk,
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buffered out port:32 p_bclk,
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//port p_lrclk,
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//port p_bclk,
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#else
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in port p_lrclk,
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in port p_bclk,
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#endif
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#endif
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unsigned int divide)
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{
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#ifndef CODEC_MASTER
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/* Output 0 on BCLK to ensure clock is low
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* Required as stop_clock will only complete when the clock is low
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*/
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configure_out_port_no_ready(p_bclk, clk_audio_mclk, 0);
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p_bclk <: 0;
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/* Stop bit and master clock blocks and clear port buffers */
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stop_clock(clk_audio_bclk);
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stop_clock(clk_audio_mclk);
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clearbuf(p_lrclk);
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clearbuf(p_bclk);
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#if (I2S_CHANS_ADC != 0)
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for(int i = 0; i < I2S_WIRES_ADC; i++)
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{
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clearbuf(p_i2s_adc[i]);
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}
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#endif
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#if (I2S_CHANS_DAC != 0)
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for(int i = 0; i < I2S_WIRES_DAC; i++)
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{
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clearbuf(p_i2s_dac[i]);
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}
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#endif
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/* Clock master clock-block from master-clock port */
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configure_clock_src(clk_audio_mclk, p_mclk);
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/* For a divide of one (i.e. bitclock == master-clock) BClk is set to clock_output mode.
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* In this mode it outputs an edge clock on every tick of itsassociated clock_block.
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*
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* For all other divides, BClk is clocked by the master clock and data
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* will be output to p_bclk to generate the bit clock.
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*/
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if (divide == 1) /* e.g. 176.4KHz from 11.2896 */
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{
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configure_port_clock_output(p_bclk, clk_audio_mclk);
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}
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else
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{
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/* bit clock port from master clock clock-clock block */
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configure_out_port_no_ready(p_bclk, clk_audio_mclk, 0);
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}
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/* Generate bit clock block from pin */
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configure_clock_src(clk_audio_bclk, p_bclk);
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#if (I2S_CHANS_DAC != 0)
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/* Clock I2S output data ports from clock block */
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for(int i = 0; i < I2S_WIRES_DAC; i++)
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{
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configure_out_port_no_ready(p_i2s_dac[i], clk_audio_bclk, 0);
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}
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#endif
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#if (I2S_CHANS_ADC != 0)
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/* Clock I2S input data ports from clock block */
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for(int i = 0; i < I2S_WIRES_ADC; i++)
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{
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configure_in_port_no_ready(p_i2s_adc[i], clk_audio_bclk);
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}
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#endif
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/* Clock LR clock from bit clock-block */
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configure_out_port_no_ready(p_lrclk, clk_audio_bclk, 0);
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/* Start clock blocks ticking */
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start_clock(clk_audio_mclk);
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start_clock(clk_audio_bclk);
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/* bclk initial state needs to be high */
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//p_bclk <: 0xFFFFFFFF;
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/* Pause until output completes */
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sync(p_bclk);
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#else /* CODEC_MASTER */
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/* Stop bit and master clock blocks */
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stop_clock(clk_audio_bclk);
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stop_clock(clk_audio_mclk);
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/* Clock master clock-block from master-clock port -
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* though not directly used in I2S slave mode it is required for FB */
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configure_clock_src(clk_audio_mclk, p_mclk);
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/* Clock bclk clock-block from bclk pin */
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configure_clock_src(clk_audio_bclk, p_bclk);
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/* Clock I2S output data ports from b-clock clock block */
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for(int i = 0; i < I2S_WIRES_DAC; i++)
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{
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configure_out_port_no_ready(p_i2s_dac[i], clk_audio_bclk, 0);
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}
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/* Clock I2S input data ports from clock block */
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for(int i = 0; i < I2S_WIRES_ADC; i++)
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{
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configure_in_port_no_ready(p_i2s_adc[i], clk_audio_bclk);
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}
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configure_in_port_no_ready(p_lrclk, clk_audio_bclk);
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start_clock(clk_audio_bclk);
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start_clock(clk_audio_mclk);
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#endif
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}
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#if 0
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void ConfigAudioPorts_dsd(unsigned int divide)
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{
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#ifndef CODEC_MASTER
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/* Output 0 on BCLK to ensure clock is low
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* Required as stop_clock will only complete when the clock is low
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*/
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//configure_out_port_no_ready(p_dsd_clk, clk_audio_bclk, 0);
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//configure_clock_src(clk_audio_mclk, p_mclk);
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configure_out_port_no_ready(p_dsd_clk, clk_audio_mclk, 0);
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p_dsd_clk <: 0;
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/* Stop bit and master clock blocks and clear port buffers */
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stop_clock(clk_audio_bclk);
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stop_clock(clk_audio_mclk);
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clearbuf(p_dsd_clk);
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clearbuf(p_dsd_left);
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clearbuf(p_dsd_right);
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/* Clock master clock-block from master-clock port */
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configure_clock_src(clk_audio_mclk, p_mclk);
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/* For a divide of one (i.e. bitclock == master-clock) BClk is set to clock_output mode.
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* In this mode it outputs an edge clock on every tick of itsassociated clock_block.
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*
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* For all other divides, BClk is clocked by the master clock and data
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* will be output to p_bclk to generate the bit clock.
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*/
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if (divide == 1) /* e.g. 176.4KHz from 11.2896 */
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{
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configure_port_clock_output(p_dsd_clk, clk_audio_mclk);
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}
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else
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{
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/* bit clock port from master clock clock-clock block */
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configure_out_port_no_ready(p_dsd_clk, clk_audio_mclk, 0);
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}
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/* bclk clock-blocked clocked by dsd_clk pin */
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configure_clock_src(clk_audio_bclk, p_dsd_clk);
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configure_out_port_no_ready(p_dsd_left, clk_audio_bclk, 0);
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configure_out_port_no_ready(p_dsd_right, clk_audio_bclk, 0);
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/* Start clock blocks ticking */
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start_clock(clk_audio_mclk);
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start_clock(clk_audio_bclk);
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/* bclk initial state needs to be high */
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p_dsd_clk<: 0xFFFFFFFF;
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/* Pause until output completes */
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sync(p_dsd_clk);
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#else /* CODEC_MASTER */
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#error CODEC MASTER for DSD not currently implemented
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#endif
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}
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#endif
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