forked from PAWPAW-Mirror/lib_xua
76 lines
2.7 KiB
Plaintext
76 lines
2.7 KiB
Plaintext
#include <xs1.h>
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#include <print.h>
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#define GLXID 0x0001
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#define XS1_GLX_PERIPH_USB_ID 0x1
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#define XS1_GLX_CFG_RST_MISC_ADRS 0x50
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#define XS1_UIFM_PHY_CONTROL_REG 0x3c
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#define XS1_UIFM_PHY_CONTROL_FORCERESET 0x0
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#define XS1_GLX_CFG_USB_CLK_EN_BASE 0x3
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#define XS1_GLX_CFG_USB_EN_BASE 0x2
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#define XS1_GLX_PERIPH_SCTH_ID 0x3
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#define XS1_UIFM_FUNC_CONTROL_REG 0xc
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#define XS1_UIFM_FUNC_CONTROL_XCVRSELECT 0x0
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#define XS1_UIFM_FUNC_CONTROL_TERMSELECT 0x1
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int write_sswitch_reg_blind(unsigned coreid, unsigned reg, unsigned data);
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void write_sswitch_reg_verify(unsigned coreid, unsigned reg, unsigned data, unsigned failval);
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int write_glx_periph_word(unsigned destId, unsigned periphAddress, unsigned destRegAddr, unsigned data);
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int write_glx_periph_reg(unsigned dest_id, unsigned periph_addr, unsigned dest_reg_addr, unsigned bad_packet, unsigned data_size, char buf[]);
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void read_sswitch_reg_verify(unsigned coreid, unsigned reg, unsigned &data, unsigned failval);
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/* Reboots XMOS device by writing to the PLL config register */
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void device_reboot_implementation(chanend spare)
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{
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//#ifdef ARCH_S
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#if 1
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unsigned wdata;
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char wdatac[1];
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write_glx_periph_word(GLXID, XS1_GLX_PERIPH_USB_ID, XS1_UIFM_FUNC_CONTROL_REG, 4);
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// (0<<XS1_UIFM_FUNC_CONTROL_XCVRSELECT)
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// | (0<<XS1_UIFM_FUNC_CONTROL_TERMSELECT));
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// Turn off All term resistors and d+ pullup
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// Term select and opmode
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#if 0
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/* Write to glx scratch reg so we know rebooting into DFU mode */
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wdatac[0] = 0x77;
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write_glx_periph_reg(GLXID, XS1_GLX_PERIPH_SCTH_ID, 0x1, 0, 1, wdatac);
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// Issue soft boot
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wdata = 0x000c0001;
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write_sswitch_reg_verify(GLXID, XS1_GLX_CFG_RST_MISC_ADRS, wdata, 2);
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while(1); // Should reset before it executes this.
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#endif
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/* Keep usb clock active, enter active mode */
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//rite_sswitch_reg(GLXID, XS1_GLX_CFG_RST_MISC_ADRS, (0 << XS1_GLX_CFG_USB_CLK_EN_BASE) | (0<<XS1_GLX_CFG_USB_EN_BASE) );
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/* Now reset the phy */
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// write_glx_periph_word(GLXID, XS1_GLX_PERIPH_USB_ID, XS1_UIFM_PHY_CONTROL_REG, (1<<XS1_UIFM_PHY_CONTROL_FORCERESET));
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/* Enable the USB clock */
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//write_sswitch_reg(GLXID, XS1_GLX_CFG_RST_MISC_ADRS, ( ( 0 << XS1_GLX_CFG_USB_CLK_EN_BASE ) ) );
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#endif
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#if 1
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outct(spare, XS1_CT_END); // have to do this before freeing the chanend
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inct(spare); // Receive end ct from usb_buffer to close down in both directions
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// Need a spare chanend so we can talk to the pll register
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asm("freer res[%0]"::"r"(spare));
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{
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unsigned int pllVal;
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unsigned int core_id = get_core_id();
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read_sswitch_reg(core_id, 6, pllVal);
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write_sswitch_reg_blind(core_id^0x8000, 6, pllVal);
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write_sswitch_reg_blind(core_id, 6, pllVal);
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}
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#endif
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}
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