forked from PAWPAW-Mirror/lib_xua
65 lines
1.6 KiB
Plaintext
65 lines
1.6 KiB
Plaintext
// Copyright (c) 2016-2018, XMOS Ltd, All rights reserved
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#ifdef SIMULATION
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#include <platform.h>
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#include <print.h>
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extern port p_mclk_in;
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extern port p_mclk25mhz;
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extern clock clk_mclk25mhz;
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void AudioHwConfig(unsigned samFreq, unsigned mClk, unsigned dsdMode, unsigned sampRes_DAC, unsigned sampRes_ADC)
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{
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// nothing
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}
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void AudioHwInit()
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{
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// nothing
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}
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extern clock clk_audio_mclk_gen;
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extern out port p_mclk_gen;
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void master_mode_clk_setup(void)
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{
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configure_clock_rate(clk_audio_mclk_gen, 25, 1); // Slighly faster than typical MCLK of 24.576MHz
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configure_port_clock_output(p_mclk_gen, clk_audio_mclk_gen);
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start_clock(clk_audio_mclk_gen);
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//printstrln("Starting mclk");
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delay_seconds(-1); //prevent destructor ruining clock gen
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}
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#if CODEC_MASTER
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extern out port p_bclk_gen;
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extern clock clk_audio_bclk_gen;
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extern out port p_lrclk_gen;
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extern clock clk_audio_lrclk_gen;
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void slave_mode_clk_setup(const unsigned samFreq, const unsigned chans_per_frame){
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const unsigned data_bits = 32;
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const unsigned mclk_freq = 24576000;
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const unsigned mclk_bclk_ratio = mclk_freq / (chans_per_frame * samFreq * data_bits);
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const unsigned bclk_lrclk_ratio = (chans_per_frame * data_bits); // 48.828Hz LRCLK
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//bclk
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configure_clock_src_divide(clk_audio_bclk_gen, p_mclk_gen, mclk_bclk_ratio/2);
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configure_port_clock_output(p_bclk_gen, clk_audio_bclk_gen);
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start_clock(clk_audio_bclk_gen);
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//lrclk
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configure_clock_src_divide(clk_audio_lrclk_gen, p_bclk_gen, bclk_lrclk_ratio/2);
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configure_port_clock_output(p_lrclk_gen, clk_audio_lrclk_gen);
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start_clock(clk_audio_lrclk_gen);
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//mclk
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master_mode_clk_setup();
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}
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#endif
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#endif
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