forked from PAWPAW-Mirror/lib_xua
86b4ab89ea
The device now adjusts it's clock to the USB clock when host is not pushing data to device.
113 lines
3.8 KiB
Plaintext
113 lines
3.8 KiB
Plaintext
#include "xua.h"
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#include <platform.h>
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#include <xs1.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <xclib.h>
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#include <stdint.h>
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#include <assert.h>
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#include "mic_array.h"
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void mic_array_decimator_set_samprate(const unsigned samplerate, int mic_decimator_fir_data_array[], mic_array_decimator_conf_common_t *dcc, mic_array_decimator_config_t dc[])
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{
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unsigned decimationfactor = 96000/samplerate;
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int fir_gain_compen[7];
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int * unsafe fir_coefs[7];
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unsafe
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{
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fir_gain_compen[0] = 0;
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fir_gain_compen[1] = FIR_COMPENSATOR_DIV_2; //48kHz
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fir_gain_compen[2] = FIR_COMPENSATOR_DIV_4;
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fir_gain_compen[3] = FIR_COMPENSATOR_DIV_6; //16kHz
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fir_gain_compen[4] = FIR_COMPENSATOR_DIV_8;
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fir_gain_compen[5] = 0;
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fir_gain_compen[6] = FIR_COMPENSATOR_DIV_12;
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fir_coefs[0] = 0;
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fir_coefs[1] = (int * unsafe)g_third_stage_div_2_fir;
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fir_coefs[2] = (int * unsafe)g_third_stage_div_4_fir;
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fir_coefs[3] = (int * unsafe)g_third_stage_div_6_fir;
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fir_coefs[4] = (int * unsafe)g_third_stage_div_8_fir;
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fir_coefs[5] = 0;
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fir_coefs[6] = (int * unsafe)g_third_stage_div_12_fir;
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//dcc = {MIC_ARRAY_MAX_FRAME_SIZE_LOG2, 1, 0, 0, decimationfactor, fir_coefs[decimationfactor/2], 0, 0, DECIMATOR_NO_FRAME_OVERLAP, 2};
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dcc->len = MIC_ARRAY_MAX_FRAME_SIZE_LOG2;
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dcc->apply_dc_offset_removal = 1;
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dcc->index_bit_reversal = 0;
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dcc->windowing_function = null;
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dcc->output_decimation_factor = decimationfactor;
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dcc->coefs = fir_coefs[decimationfactor/2];
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dcc->apply_mic_gain_compensation = 0;
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dcc->fir_gain_compensation = fir_gain_compen[decimationfactor/2];
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dcc->buffering_type = DECIMATOR_NO_FRAME_OVERLAP;
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dcc->number_of_frame_buffers = 2;
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//dc[0] = {&dcc, mic_decimator_fir_data[0], {0, 0, 0, 0}, 4};
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dc[0].dcc = dcc;
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dc[0].data = mic_decimator_fir_data_array;
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dc[0].mic_gain_compensation[0]=0;
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dc[0].mic_gain_compensation[1]=0;
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dc[0].mic_gain_compensation[2]=0;
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dc[0].mic_gain_compensation[3]=0;
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dc[0].channel_count = 4;
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}
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}
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#if MAX_FREQ > 48000
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#error MAX_FREQ > 48000 NOT CURRENTLY SUPPORTED
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#endif
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void pdm_mic(streaming chanend c_ds_output, in buffered port:32 p_pdm_mics)
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{
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streaming chan c_4x_pdm_mic_0;
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assert((MCLK_48 / 3072000) == (MCLK_441 / 2822400)); //Make sure mic clock is achievable from MCLK
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par
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{
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mic_array_pdm_rx(p_pdm_mics, c_4x_pdm_mic_0, null);
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mic_array_decimate_to_pcm_4ch(c_4x_pdm_mic_0, c_ds_output, MIC_ARRAY_NO_INTERNAL_CHANS);
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}
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}
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void mic_array_setup_ddr(clock pdmclk,
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clock pdmclk6,
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in port p_mclk, /*used only in I2S slave case*/
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out port p_pdm_clk,
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buffered in port:32 p_pdm_data,
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int divide) {
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#if !XUA_ADAPTIVE //i2s slave
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//p_mclk coming from the Pi is 24.576 MHz
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configure_clock_src_divide(pdmclk, p_mclk, 4); //3.072 = 24.576 / 8
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configure_clock_src_divide(pdmclk6, p_mclk, 2); //6.144 = 24.576 / 4
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#else
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configure_clock_xcore(pdmclk, 80); // 3.072
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configure_clock_xcore(pdmclk6, 40); // 6.144
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#endif
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configure_port_clock_output(p_pdm_clk, pdmclk);
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configure_in_port(p_pdm_data, pdmclk6);
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/* start the faster capture clock */
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start_clock(pdmclk6);
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/* wait for a rising edge on the capture clock */
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partin(p_pdm_data, 4);
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/* start the slower output clock */
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start_clock(pdmclk);
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/*
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* this results in the rising edge of the capture clock
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* leading the rising edge of the output clock by one period
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* of p_mclk, which is about 40.7 ns for the typical frequency
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* of 24.576 megahertz.
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* This should fall within the data valid window.
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*/
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}
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