forked from PAWPAW-Mirror/lib_xua
badcb71c80
- Use app PLL for sync mode - Use app PLL on xcore.ai devices by default (unless ADAT or SPDIF receive enabled) - Added XUA_USE_APP_PLL (which is default 1) - Some tidy of xua_conf_default.h - Added DEFAULT_MCLK define
49 lines
1.5 KiB
C
49 lines
1.5 KiB
C
// Copyright 2011-2023 XMOS LIMITED.
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// This Software is subject to the terms of the XMOS Public Licence: Version 1.
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#ifndef _CLOCKING_H_
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#define _CLOCKING_H_
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#include <xs1.h>
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#include "xua.h"
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interface pll_ref_if
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{
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void toggle();
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void init();
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void toggle_timed(int relative);
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};
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[[distributable]]
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void PllRefPinTask(server interface pll_ref_if i_pll_ref, out port p_sync);
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/** Clock generation and digital audio I/O handling.
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*
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* \param c_spdif_rx channel connected to S/PDIF receive thread
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* \param c_adat_rx channel connect to ADAT receive thread
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* \param i_pll_ref interface to taslk that outputs clock signal to drive external frequency synthesizer
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* \param c_audio channel connected to the audio() thread
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* \param c_clk_ctl channel connected to Endpoint0() for configuration of the
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* clock
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* \param c_clk_int channel connected to the decouple() thread for clock
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interrupts
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*/
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void clockGen(streaming chanend ?c_spdif_rx, chanend ?c_adat_rx, client interface pll_ref_if i_pll_ref, chanend c_audio, chanend c_clk_ctl, chanend c_clk_int);
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#if (XUA_USE_APP_PLL)
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struct PllSettings
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{
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// Count we expect on MCLK port timer at SW PLL check point.
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// Note, we expect wrapping so this is essentiually a modulus
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unsigned adder;
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unsigned fracIdx;
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int firstUpdate;
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};
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void AppPllEnable(tileref tile, int mclkFreq_hz);
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void AppPllGetSettings(int clkFreq_hz, struct PllSettings &pllSettings);
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void AppPllUpdate(tileref tile, unsigned short mclk_pt, struct PllSettings &pllSettings);
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#endif
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#endif
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