forked from PAWPAW-Mirror/lib_xua
372 lines
13 KiB
Plaintext
372 lines
13 KiB
Plaintext
// Copyright (c) 2016-2018, XMOS Ltd, All rights reserved
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#ifdef HARDWARE
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#include <xs1.h>
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#include <assert.h>
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#include "devicedefines.h"
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#include <platform.h>
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#include "gpio_access.h"
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#include "i2c_shared.h"
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#include "cs4384.h"
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#include "cs5368.h"
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#include "cs2100.h"
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#include "print.h"
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#include "dsd_support.h"
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/* The number of timer ticks to wait for the audio PLL to lock */
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/* CS2100 lists typical lock time as 100 * input period */
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#define AUDIO_PLL_LOCK_DELAY (40000000)
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#if defined(SPDIF_RX) || defined(ADAT_RX)
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#define USE_FRACTIONAL_N 1
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#endif
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on tile[0] : out port p_gpio = XS1_PORT_8C;
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#ifndef IAP
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/* If IAP not enabled, i2c ports not declared - still needs for DAC config */
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on tile [0] : struct r_i2c r_i2c = {XS1_PORT_4A};
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#else
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extern struct r_i2c r_i2c;
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#endif
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#define DAC_REGWRITE(reg, val) {data[0] = val; i2c_shared_master_write_reg(r_i2c, CS4384_I2C_ADDR, reg, data, 1);}
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#define DAC_REGREAD(reg, val) {i2c_shared_master_read_reg(r_i2c, CS4384_I2C_ADDR, reg, val, 1);}
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#define ADC_REGWRITE(reg, val) {data[0] = val; i2c_shared_master_write_reg(r_i2c, CS5368_I2C_ADDR, reg, data, 1);}
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#ifdef USE_FRACTIONAL_N
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#if !(defined(SPDIF_RX) || defined(ADAT_RX))
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/* Choose a frequency the xcore can easily generate internally */
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#define PLL_SYNC_FREQ 1000000
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#else
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#define PLL_SYNC_FREQ 300
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#endif
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#define CS2100_REGREAD(reg, data) {data[0] = 0xAA; i2c_master_read_reg(CS2100_I2C_DEVICE_ADDR, reg, data, 1, r_i2c);}
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#define CS2100_REGREAD_ASSERT(reg, data, expected) {data[0] = 0xAA; i2c_master_read_reg(CS2100_I2C_DEVICE_ADDR, reg, data, 1, r_i2c); assert(data[0] == expected);}
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#define CS2100_REGWRITE(reg, val) {data[0] = val; i2c_master_write_reg(CS2100_I2C_DEVICE_ADDR, reg, data, 1, r_i2c);}
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/* Init of CS2100 */
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void PllInit(void)
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{
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unsigned char data[1] = {0};
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#if XCORE_200_MC_AUDIO_HW_VERSION < 2
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/* Enable init */
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CS2100_REGWRITE(CS2100_DEVICE_CONFIG_1, 0x05);
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#else
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CS2100_REGWRITE(CS2100_DEVICE_CONFIG_1, 0x07);
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#endif
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CS2100_REGWRITE(CS2100_GLOBAL_CONFIG, 0x01);
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CS2100_REGWRITE(CS2100_FUNC_CONFIG_1, 0x08);
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CS2100_REGWRITE(CS2100_FUNC_CONFIG_2, 0x00); //0x10 for always gen clock even when unlocked
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/* Read back and check */
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#if XCORE_200_MC_AUDIO_HW_VERSION < 2
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CS2100_REGREAD_ASSERT(CS2100_DEVICE_CONFIG_1, data, 0x05);
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#else
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CS2100_REGREAD_ASSERT(CS2100_DEVICE_CONFIG_1, data, 0x07);
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#endif
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CS2100_REGREAD_ASSERT(CS2100_GLOBAL_CONFIG, data, 0x01);
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CS2100_REGREAD_ASSERT(CS2100_FUNC_CONFIG_1, data, 0x08);
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CS2100_REGREAD_ASSERT(CS2100_FUNC_CONFIG_2, data, 0x00);
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}
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/* Setup PLL multiplier */
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void PllMult(unsigned output, unsigned ref)
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{
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unsigned char data[1] = {0};
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/* PLL expects 12:20 format, convert output and ref to 12:20 */
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/* Shift up the dividend by 12 to retain format... */
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unsigned mult = (unsigned) ((((unsigned long long)output) << 32) / (((unsigned long long)ref) << 20));
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CS2100_REGWRITE(CS2100_RATIO_1, (mult >> 24) & 0xFF);
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CS2100_REGWRITE(CS2100_RATIO_2, (mult >> 16) & 0xFF);
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CS2100_REGWRITE(CS2100_RATIO_3, (mult >> 8) & 0xFF);
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CS2100_REGWRITE(CS2100_RATIO_4, (mult & 0xFF));
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/* Read back and check */
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CS2100_REGREAD_ASSERT(CS2100_RATIO_1, data, ((mult >> 24) & 0xFF));
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CS2100_REGREAD_ASSERT(CS2100_RATIO_2, data, ((mult >> 16) & 0xFF));
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CS2100_REGREAD_ASSERT(CS2100_RATIO_3, data, ((mult >> 8) & 0xFF));
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CS2100_REGREAD_ASSERT(CS2100_RATIO_4, data, (mult & 0xFF));
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}
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#endif
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#if !(defined(SPDIF_RX) || defined(ADAT_RX)) && defined(USE_FRACTIONAL_N)
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on tile[AUDIO_IO_TILE] : out port p_pll_clk = PORT_PLL_REF;
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on tile[AUDIO_IO_TILE] : clock clk_pll_sync = XS1_CLKBLK_5;
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#endif
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void wait_us(int microseconds)
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{
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timer t;
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unsigned time;
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t :> time;
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t when timerafter(time + (microseconds * 100)) :> void;
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}
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void AudioHwInit(chanend ?c_codec)
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{
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#if !(defined(SPDIF_RX) || defined(ADAT_RX)) && defined(USE_FRACTIONAL_N)
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/* Output a fixed sync clock to the pll */
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configure_clock_rate(clk_pll_sync, 100, 100/(PLL_SYNC_FREQ/1000000));
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configure_port_clock_output(p_pll_clk, clk_pll_sync);
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start_clock(clk_pll_sync);
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#endif
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/* Init the i2c module */
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i2c_shared_master_init(r_i2c);
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/* Assert reset to ADC and DAC */
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set_gpio(P_GPIO_DAC_RST_N, 0);
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set_gpio(P_GPIO_ADC_RST_N, 0);
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/* 0b11 : USB B */
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/* 0b01 : Lightning */
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/* 0b10 : USB A */
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#ifdef USB_SEL_A
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set_gpio(P_GPIO_USB_SEL0, 0);
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set_gpio(P_GPIO_USB_SEL1, 1);
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#else
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set_gpio(P_GPIO_USB_SEL0, 1);
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set_gpio(P_GPIO_USB_SEL1, 1);
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#endif
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#ifdef USE_FRACTIONAL_N
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/* If we have any digital input then use the external PLL - selected via MUX */
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set_gpio(P_GPIO_PLL_SEL, 1);
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/* Initialise external PLL */
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PllInit();
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#endif
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#ifdef IAP
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/* Enable VBUS output */
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set_gpio(P_GPIO_VBUS_EN, 1);
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#endif
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}
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/* Configures the external audio hardware for the required sample frequency.
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* See gpio.h for I2C helper functions and gpio access
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*/
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void AudioHwConfig(unsigned samFreq, unsigned mClk, chanend ?c_codec, unsigned dsdMode,
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unsigned sampRes_DAC, unsigned sampRes_ADC)
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{
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unsigned char data[1] = {0};
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/* Put ADC and DAC into reset */
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set_gpio(P_GPIO_ADC_RST_N, 0);
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set_gpio(P_GPIO_DAC_RST_N, 0);
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/* Set master clock select appropriately */
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#if defined(USE_FRACTIONAL_N)
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/* Configure external fractional-n clock multiplier for 300Hz -> mClkFreq */
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PllMult(mClk, PLL_SYNC_FREQ);
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#endif
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/* Allow some time for mclk to lock and MCLK to stabilise - this is important to avoid glitches at start of stream */
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{
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timer t;
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unsigned time;
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t :> time;
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t when timerafter(time+AUDIO_PLL_LOCK_DELAY) :> void;
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}
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#if defined(USE_FRACTIONAL_N)
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while(1)
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{
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/* Read Unlock Indicator in PLL as sanity check... */
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CS2100_REGREAD(CS2100_DEVICE_CONTROL, data);
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if(!(data[0] & 0x80))
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{
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break;
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}
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}
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#else
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if (mClk == MCLK_441)
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{
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set_gpio(P_GPIO_MCLK_FSEL, 0);
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}
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else
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{
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set_gpio(P_GPIO_MCLK_FSEL, 1); //mClk = MCLK_48
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}
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/* Allow MCLK to settle */
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wait_us(20000);
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#endif
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#if 1
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if((dsdMode == DSD_MODE_NATIVE) || (dsdMode == DSD_MODE_DOP))
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{
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/* Enable DSD 8ch out mode on mux */
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//set_gpio(p_adrst_cksel_dsd, P_DSD_MODE, 1);
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/* DAC out out reset, note ADC left in reset in for DSD mode */
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set_gpio(P_GPIO_DAC_RST_N, 1);
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/* Configure DAC values required for DSD mode */
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/* Mode Control 1 (Address: 0x02) */
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/* bit[7] : Control Port Enable (CPEN) : Set to 1 for enable
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* bit[6] : Freeze controls (FREEZE) : Set to 1 for freeze
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* bit[5] : PCM/DSD Selection (DSD/PCM) : Set to 1 for DSD
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* bit[4:1] : DAC Pair Disable (DACx_DIS) : All Dac Pairs enabled
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* bit[0] : Power Down (PDN) : Powered down
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*/
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DAC_REGWRITE(CS4384_MODE_CTRL, 0xe1);
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if (samFreq > 3000000)
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{
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/* DSD128 */
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/* DSD Control (Address: 0x04) */
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/* bit[7:5] : DSD Digital Inteface Format (DSD_DIF) : 128x over samples with 4x MCLK
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* bit[4] : Direct DSD Conversion: Set to 0, data sent to DSD processor
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* bit[3] : Static DSD detect : 1 for enabled
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* bit[2] : Invalid DSD Detect : 1 for enabled
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* bit[1] : DSD Phase Modulation Mode Select
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* bit[0] : DSD Phase Modulation Enable
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*/
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DAC_REGWRITE(CS4384_DSD_CTRL, 0b11001100);
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}
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else
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{
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/* DSD64 */
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/* DSD Control (Address: 0x04) */
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/* bit[7:5] : DSD Digital Inteface Format (DSD_DIF) : 64x over samples with 8x MCLK
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* bit[4] : Direct DSD Conversion: Set to 0, data sent to DSD processor
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* bit[3] : Static DSD detect : 1 for enabled
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* bit[2] : Invalid DSD Detect : 1 for enabled
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* bit[1] : DSD Phase Modulation Mode Select
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* bit[0] : DSD Phase Modulation Enable
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*/
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DAC_REGWRITE(CS4384_DSD_CTRL, 0b01001100);
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}
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/* Mode Control 1 (Address: 0x02) */
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/* bit[7] : Control Port Enable (CPEN) : Set to 1 for enable
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* bit[6] : Freeze controls (FREEZE) : Set to 0 for not freeze
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* bit[5] : PCM/DSD Selection (DSD/PCM) : Set to 1 for DSD
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* bit[4:1] : DAC Pair Disable (DACx_DIS) : All Dac Pairs enabled
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* bit[0] : Power Down (PDN) : Power down disabled
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*/
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DAC_REGWRITE(CS4384_MODE_CTRL, 0xA0);
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/* Note: ADC kept in reset, no config sent. DSD mode is output only 0*/
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}
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else
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{
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/* dsdMode == 0 */
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/* Set MUX to PCM mode (muxes ADC I2S data lines) */
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set_gpio(P_GPIO_DSD_MODE, 0);
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/* Take ADC out of reset */
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set_gpio(P_GPIO_ADC_RST_N, 1);
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{
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unsigned dif = 0, mode = 0;
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#ifdef I2S_MODE_TDM
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dif = 0x02; /* TDM */
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#else
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dif = 0x01; /* I2S */
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#endif
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#ifdef CODEC_MASTER
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/* Note, only the ADC device supports being I2S master.
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* Set ADC as master and run DAC as slave */
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if(samFreq < 54000)
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mode = 0x00; /* Single-speed Mode Master */
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else if(samFreq < 108000)
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mode = 0x01; /* Double-speed Mode Master */
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else if(samFreq < 216000)
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mode = 0x02; /* Quad-speed Mode Master */
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#else
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mode = 0x03; /* Slave mode all speeds */
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#endif
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/* Reg 0x01: (GCTL) Global Mode Control Register */
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/* Bit[7]: CP-EN: Manages control-port mode
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* Bit[6]: CLKMODE: Setting puts part in 384x mode
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* Bit[5:4]: MDIV[1:0]: Set to 01 for /2
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* Bit[3:2]: DIF[1:0]: Data Format: 0x01 for I2S, 0x02 for TDM
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* Bit[1:0]: MODE[1:0]: Mode: 0x11 for slave mode
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*/
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ADC_REGWRITE(CS5368_GCTL_MDE, 0b10010000 | (dif << 2) | mode);
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}
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/* Reg 0x06: (PDN) Power Down Register */
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/* Bit[7:6]: Reserved
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* Bit[5]: PDN-BG: When set, this bit powers-own the bandgap reference
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* Bit[4]: PDM-OSC: Controls power to internal oscillator core
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* Bit[3:0]: PDN: When any bit is set all clocks going to that channel pair are turned off
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*/
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ADC_REGWRITE(CS5368_PWR_DN, 0b00000000);
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#ifdef CODEC_MASTER
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/* Allow some time for clocks from ADC to become stable */
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wait_us(500);
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#endif
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/* Configure DAC with PCM values. Note 2 writes to mode control to enable/disable freeze/power down */
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set_gpio(P_GPIO_DAC_RST_N, 1);//De-assert DAC reset
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wait_us(500);
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/* Mode Control 1 (Address: 0x02) */
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/* bit[7] : Control Port Enable (CPEN) : Set to 1 for enable
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* bit[6] : Freeze controls (FREEZE) : Set to 1 for freeze
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* bit[5] : PCM/DSD Selection (DSD/PCM) : Set to 0 for PCM
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* bit[4:1] : DAC Pair Disable (DACx_DIS) : All Dac Pairs enabled
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* bit[0] : Power Down (PDN) : Powered down
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*/
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DAC_REGWRITE(CS4384_MODE_CTRL, 0b11000001);
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#ifdef I2S_MODE_TDM
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/* PCM Control (Address: 0x03) */
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/* bit[7:4] : Digital Interface Format (DIF) : 0b1100 for TDM
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* bit[3:2] : Reserved
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* bit[1:0] : Functional Mode (FM) : 0x11 for auto-speed detect (32 to 200kHz)
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*/
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DAC_REGWRITE(CS4384_PCM_CTRL, 0b11000011);
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#else
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/* PCM Control (Address: 0x03) */
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/* bit[7:4] : Digital Interface Format (DIF) : 0b0001 for I2S up to 24bit
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* bit[3:2] : Reserved
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* bit[1:0] : Functional Mode (FM) : 0x00 - single-speed mode (4-50kHz)
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* : 0x01 - double-speed mode (50-100kHz)
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* : 0x10 - quad-speed mode (100-200kHz)
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* : 0x11 - auto-speed detect (32 to 200kHz)
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* (note, some Mclk/SR ratios not supported in auto)
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*
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*/
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unsigned char regVal = 0;
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if(samFreq < 50000)
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regVal = 0b00010100;
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else if(samFreq < 100000)
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regVal = 0b00010101;
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else //if(samFreq < 200000)
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regVal = 0b00010110;
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DAC_REGWRITE(CS4384_PCM_CTRL, regVal);
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#endif
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/* Mode Control 1 (Address: 0x02) */
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/* bit[7] : Control Port Enable (CPEN) : Set to 1 for enable
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* bit[6] : Freeze controls (FREEZE) : Set to 0 for freeze
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* bit[5] : PCM/DSD Selection (DSD/PCM) : Set to 0 for PCM
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* bit[4:1] : DAC Pair Disable (DACx_DIS) : All Dac Pairs enabled
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* bit[0] : Power Down (PDN) : Not powered down
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*/
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DAC_REGWRITE(CS4384_MODE_CTRL, 0b10000000);
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}
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#endif
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return;
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}
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//:
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#endif
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