forked from PAWPAW-Mirror/lib_xua
53 lines
1.8 KiB
C
53 lines
1.8 KiB
C
// Copyright (c) 2016-2018, XMOS Ltd, All rights reserved
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#ifndef __gpio_access_h__
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#define __gpio_access_h__
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#include "customdefines.h"
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#if XCORE_200_MC_AUDIO_HW_VERSION == 2
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/* General output port bit definitions */
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#define P_GPIO_DSD_MODE (1 << 0) /* DSD mode select 0 = 8i/8o I2S, 1 = 8o DSD*/
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#define P_GPIO_DAC_RST_N (1 << 1)
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#define P_GPIO_USB_SEL0 (1 << 2)
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#define P_GPIO_USB_SEL1 (1 << 3)
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#define P_GPIO_VBUS_EN (1 << 4)
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#define P_GPIO_PLL_SEL (1 << 5) /* 1 = CS2100, 0 = Phaselink clock source */
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#define P_GPIO_ADC_RST_N (1 << 6)
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#define P_GPIO_MCLK_FSEL (1 << 7) /* Select frequency on Phaselink clock. 0 = 24.576MHz for 48k, 1 = 22.5792MHz for 44.1k.*/
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#else
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/* General output port bit definitions */
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#define P_GPIO_DSD_MODE (1 << 0) /* DSD mode select 0 = 8i/8o I2S, 1 = 8o DSD*/
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#define P_GPIO_DAC_RST_N (1 << 1)
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#define P_GPIO_ADC_RST_N (1 << 2)
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#define P_GPIO_USB_SEL0 (1 << 3)
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#define P_GPIO_USB_SEL1 (1 << 4)
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#define P_GPIO_VBUS_EN (1 << 5)
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#define P_GPIO_MCLK_FSEL (1 << 6) /* Select frequency on Phaselink clock. 0 = 24.576MHz for 48k, 1 = 22.5792MHz for 44.1k.*/
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#define P_GPIO_PLL_SEL (1 << 7) /* 1 = CS2100, 0 = Phaselink clock source */
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#endif
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/*LED array defines*/
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#define LED_ALL_ON 0xf00f
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#define LED_SQUARE_BIG 0x9009
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#define LED_SQUARE_SML 0x6006
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#define LED_ROW_1 0xf001
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#define LED_ROW_2 0xf003
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#define LED_ROW_3 0xf007
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#define ALL_OFF 0x0000
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// LED array masks
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#define LED_MASK_COL_OFF 0x7fff
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#define LED_MASK_DISABLE 0xffff
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void set_gpio(unsigned bit, unsigned value);
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void p_gpio_lock();
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void p_gpio_unlock();
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unsigned p_gpio_peek();
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void p_gpio_out(unsigned x);
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#endif // __gpio_access_h__
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