forked from PAWPAW-Mirror/lib_xua
64 lines
3.6 KiB
ReStructuredText
Executable File
64 lines
3.6 KiB
ReStructuredText
Executable File
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.. _usb_audio_sec_clock_recovery:
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External Clock Recovery (Clock Gen)
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===================================
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To provide an audio master clock an application may use selectable oscillators, clock
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generation IC or, in the case of xCORE.ai devices, integrated secondary PLL, to generate fixed
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master clock frequencies.
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It may also use an external PLL/Clock Multiplier to generate a master clock based on a reference from
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the xCORE.
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Using an external PLL/Clock Multiplier allows an Asynchronous mode design to lock to an external
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clock source from a digital stream (e.g. S/PDIF or ADAT input). The codebase supports the Cirrus
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Logic CS2100 device or use of lib_sw_pll (xcore.ai only) for this purpose. Other devices may be
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supported via code modification.
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The Clock Recovery core (Clock Gen) is responsible for either generating the reference frequency
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to the CS2100 device or driving lib_sw_pll from time measurements based on the local master clock
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and the time of received samples. Clock Gen (via CS2100 or lib_sw_pll) generates the master clock
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used over the whole design. This core also serves as a smaller buffer between ADAT and S/PDIF
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receiving cores and the Audio Hub core.
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When using lib_sw_pll (xcore.ai only) an further core is instantiated which performs the sigma-delta
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modulation of the xCORE PLL to ensure the lowest jitter over the audio band. See lib_sw_pll
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documentation for further details.
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When running in *Internal Clock* mode this core simply generates this clock using a local
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timer, based on the XMOS reference clock.
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When running in an external clock mode (i.e. S/PDIF Clock" or "ADAT Clock" mode) samples are
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received from the S/PDIF and/or ADAT receive core. The external frequency is calculated through
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counting samples in a given period. Either the reference clock to the CS2100 is then generated based on
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the reception of these samples or the timing information is provided to lib_sw_pll to generate
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the phase-locked clock on-chip (xcore.ai only).
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If an external stream becomes invalid, the *Internal Clock* timer event will fire to ensure that
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valid master clock generation continues regardless of cable unplugs etc. Efforts are made to
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ensure the transition between these clocks are relatively seamless. Additionally efforts are also
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made to try and keep the jitter on the reference clock as low as possible, regardless of activity
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level of the Clock Gen core. The is achieved though the use of port times to schedule pin toggling
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rather than directly outputting to the port in the case of using the CS2100. For lib_sw_pll cases the
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last setting is kept for the sigma-delta modulator ensuring clock continuity.
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The Clock Gen core gets clock selection Get/Set commands from Endpoint 0 via the ``c_clk_ctl``
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channel. This core also records the validity of external clocks, which is also queried
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through the same channel from Endpoint 0. Note, the *Internal Clock* is always reported as being
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valid. It should be noted that the device always reports the current device sample rate regardless
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of the clock being interrogated. This results in improved user experience for most driver/operating
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system combinations
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To inform the host of any status change, the Clock Gen core can also cause the Decouple core to
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request an interrupt packet on change of clock validity. This functionality is based on the Audio
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Class 2.0 status/interrupt endpoint feature.
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.. note::
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When running in Synchronous mode external digital input streams are currently not supported.
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Such a feature would require sample-rate conversion to covert from the S/PDIF or ADAT clock
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domain to the USB host clock domain. As such this core is not used in a Synchronous mode device.
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