Created xua_buffer.h.

Added dummy hw config calls to simple app.
Tmp added gpio_access

examples/app_xua_simple/src/gpio_access.c

@@ -0,0 +1,50 @@
+#include "gpio_access.h"
+//#include "swlock.h"
+#include <xs1.h>
+
+//swlock_t gpo_swlock = SWLOCK_INITIAL_VALUE;
+
+void p_gpio_lock()
+{
+    //swlock_acquire(&gpo_swlock);
+}
+
+void p_gpio_unlock()
+{
+    //swlock_release(&gpo_swlock);
+}
+
+unsigned p_gpio_peek()
+{
+    unsigned portId, x;
+
+    // Wrapped in lock to ensure it's safe from multiple logical cores
+   // swlock_acquire(&gpo_swlock);
+
+    asm("ldw %0, dp[p_gpio]":"=r"(portId));
+    asm volatile("peek %0, res[%1]":"=r"(x):"r"(portId));
+
+    return x;
+}
+
+void p_gpio_out(unsigned x)
+{
+    unsigned portId;
+
+    asm("ldw %0, dp[p_gpio]":"=r"(portId));
+    asm volatile("out res[%0], %1"::"r"(portId),"r"(x));
+
+    // Wrapped in lock to ensure it's safe from multiple logical cores
+    //swlock_release(&gpo_swlock);
+}
+
+void set_gpio(unsigned bit, unsigned value)
+{
+	unsigned port_shadow;
+	port_shadow = p_gpio_peek();         // Read port pin value
+	if (value == 0) port_shadow &= ~bit; // If writing a 0, generate mask and AND with current val
+	else port_shadow |= bit;             // Else use mask and OR to set bit
+	p_gpio_out(port_shadow);             // Write back to port. Will make port an output if not already
+}
+
+

examples/app_xua_simple/src/gpio_access.h

@@ -0,0 +1,51 @@
+#ifndef _GPIO_ACCESS_H_
+#define _GPIO_ACCESS_H_
+
+#include "customdefines.h"
+
+#if XCORE_200_MC_AUDIO_HW_VERSION == 2
+
+/* General output port bit definitions */
+#define P_GPIO_DSD_MODE         (1 << 0) /* DSD mode select 0 = 8i/8o I2S, 1 = 8o DSD*/
+#define P_GPIO_DAC_RST_N        (1 << 1)
+#define P_GPIO_USB_SEL0         (1 << 2)
+#define P_GPIO_USB_SEL1         (1 << 3)
+#define P_GPIO_VBUS_EN          (1 << 4)
+#define P_GPIO_PLL_SEL          (1 << 5) /* 1 = CS2100, 0 = Phaselink clock source */
+#define P_GPIO_ADC_RST_N        (1 << 6)
+#define P_GPIO_MCLK_FSEL        (1 << 7) /* Select frequency on Phaselink clock. 0 = 24.576MHz for 48k, 1 = 22.5792MHz for 44.1k.*/
+
+#else
+
+/* General output port bit definitions */
+#define P_GPIO_DSD_MODE         (1 << 0) /* DSD mode select 0 = 8i/8o I2S, 1 = 8o DSD*/
+#define P_GPIO_DAC_RST_N        (1 << 1)
+#define P_GPIO_ADC_RST_N        (1 << 2)
+#define P_GPIO_USB_SEL0         (1 << 3)
+#define P_GPIO_USB_SEL1         (1 << 4)
+#define P_GPIO_VBUS_EN          (1 << 5)
+#define P_GPIO_MCLK_FSEL        (1 << 6) /* Select frequency on Phaselink clock. 0 = 24.576MHz for 48k, 1 = 22.5792MHz for 44.1k.*/
+#define P_GPIO_PLL_SEL          (1 << 7) /* 1 = CS2100, 0 = Phaselink clock source */
+
+#endif
+
+
+/*LED array defines*/
+#define LED_ALL_ON              0xf00f
+#define LED_SQUARE_BIG          0x9009
+#define LED_SQUARE_SML          0x6006
+#define LED_ROW_1               0xf001
+#define LED_ROW_2               0xf003
+#define LED_ROW_3               0xf007
+#define ALL_OFF                 0x0000
+// LED array masks
+#define LED_MASK_COL_OFF        0x7fff
+#define LED_MASK_DISABLE        0xffff
+
+void set_gpio(unsigned bit, unsigned value);
+void p_gpio_lock();
+void p_gpio_unlock();
+unsigned p_gpio_peek();
+void p_gpio_out(unsigned x);
+
+#endif

examples/app_xua_simple/src/hwsupport.xc

@@ -3,6 +3,8 @@
 #include <platform.h>
 #include "audiohw.h"
 #include "customdefines.h"
+#include "gpio_access.h"
+
 
 void AudioHwConfig(unsigned samFreq, unsigned mClk, chanend ?c_codec, unsigned dsdMode,
     unsigned sampRes_DAC, unsigned sampRes_ADC)
@@ -12,6 +14,7 @@ void AudioHwConfig(unsigned samFreq, unsigned mClk, chanend ?c_codec, unsigned d
 
 void AudioHwInit(chanend ?c_codec)
 {
-  // nothing
+    set_gpio(P_GPIO_USB_SEL0, 1);
+    set_gpio(P_GPIO_USB_SEL1, 1);
 }