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Started adding adat rx to main

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This commit is contained in:
Ross Owen
2014-07-30 10:38:17 +01:00
parent b9dd030de0
commit 31004271c6
1 changed files with 33 additions and 2 deletions
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35
module_usb_audio/main.xc
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@@ -34,9 +34,13 @@
#ifdef SPDIF_RX #ifdef SPDIF_RX
#include "SpdifReceive.h" #include "SpdifReceive.h"
#include "clocking.h"
#endif #endif
#ifdef ADAT_RX
#include "adatreceiver.h"
#endif
#include "clocking.h"
/* Audio I/O - Port declarations */ /* Audio I/O - Port declarations */
#if I2S_WIRES_DAC > 0 #if I2S_WIRES_DAC > 0
@@ -130,8 +134,16 @@ on tile[XUD_TILE] : in port p_for_mclk_count = PORT_MCLK_COUNT;
on tile[AUDIO_IO_TILE] : buffered out port:32 p_spdif_tx = PORT_SPDIF_OUT; on tile[AUDIO_IO_TILE] : buffered out port:32 p_spdif_tx = PORT_SPDIF_OUT;
#endif #endif
#ifdef ADAT_RX
on stdcore[XUD_TILE] : buffered in port:32 p_adat_rx = PORT_ADAT_IN;
#endif
#ifdef SPDIF_RX #ifdef SPDIF_RX
on tile[XUD_TILE] : buffered in port:4 p_spdif_rx = PORT_SPDIF_IN; /* K: coax, J: optical */ on tile[XUD_TILE] : buffered in port:4 p_spdif_rx = PORT_SPDIF_IN;
#endif
#if defined (SPDIF_RX) || defined (ADAT_RX)
/* Reference to external clock multiplier */
on tile[AUDIO_IO_TILE] : out port p_pll_clk = PORT_PLL_REF; on tile[AUDIO_IO_TILE] : out port p_pll_clk = PORT_PLL_REF;
#endif #endif
@@ -158,6 +170,11 @@ on tile[AUDIO_IO_TILE] : clock clk_mst_spd = CLKBLK_SPDIF_TX;
on tile[XUD_TILE] : clock clk_spd_rx = CLKBLK_SPDIF_RX; on tile[XUD_TILE] : clock clk_spd_rx = CLKBLK_SPDIF_RX;
#endif #endif
#ifdef ADAT_RX
on tile[XUD_TILE] : clock clk_adat_rx = CLKBLK_ADAT_RX;
#endif
on tile[AUDIO_IO_TILE] : clock clk_audio_mclk = CLKBLK_MCLK; /* Master clock */ on tile[AUDIO_IO_TILE] : clock clk_audio_mclk = CLKBLK_MCLK; /* Master clock */
#if(AUDIO_IO_TILE != XUD_TILE) #if(AUDIO_IO_TILE != XUD_TILE)
@@ -498,6 +515,20 @@ int main()
SpdifReceive(p_spdif_rx, c_spdif_rx, 1, clk_spd_rx); SpdifReceive(p_spdif_rx, c_spdif_rx, 1, clk_spd_rx);
} }
#endif #endif
#ifdef ADAT_RX
on stdcore[0] :
{
set_thread_fast_mode_on();
set_port_clock(p_adat_rx, clk_adat_rx);
start_clock(clk_adat_rx);
while (1)
{
adatReceiver48000(p_adat_rx, c_adat_rx);
adatReceiver44100(p_adat_rx, c_adat_rx);
}
}
#endif
USER_MAIN_CORES USER_MAIN_CORES
} }