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Put USB on tile[1] - builds + I2S looping

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This commit is contained in:
Ed Clarke
2018-10-26 11:46:51 +01:00
parent 161b934b8f
commit 35042e742f
5 changed files with 46 additions and 45 deletions
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54
examples/xua_lite_example/src/app_xua_lite.xc
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@@ -23,9 +23,6 @@ on tile[0]: out port p_bclk = XS1_PORT_1P; //I2S L/R-clo
// Master clock for the audio IO tile
on tile[0]: in port p_mclk_in = XS1_PORT_1K;
// Resources for USB feedback
on tile[0]: in port p_for_mclk_count= XS1_PORT_16A; // Extra port for counting master clock ticks
// [0] : DAC_RESET_N
// [1] : I2C_INTERRUPT_N
// [2] : MUTE_EN
@@ -34,12 +31,15 @@ on tile[0]: out port p_gpio = XS1_PORT_4D;
on tile[1]: port p_scl = XS1_PORT_1C;
on tile[1]: port p_sda = XS1_PORT_1D;
on tile[1]: in port p_mclk_in_usb = XS1_PORT_1A;
on tile[1]: in port p_for_mclk_count= XS1_PORT_16A; // Extra port for counting master clock ticks
on tile[1]: clock clk_usb_mclk = XS1_CLKBLK_3; // Master clock
// Clock-block declarations
clock clk_audio_bclk = on tile[0]: XS1_CLKBLK_2; // Bit clock
clock clk_audio_mclk = on tile[0]: XS1_CLKBLK_3; // Master clock
//XUD uses XS1_CLKBLK_4, XS1_CLKBLK_5
on tile[0]:clock clk_audio_bclk = XS1_CLKBLK_2; // Bit clock
on tile[0]:clock clk_audio_mclk = XS1_CLKBLK_3; // Master clock
//XUD uses XS1_CLKBLK_4, XS1_CLKBLK_5 on tile[1]
// Endpoint type tables - informs XUD what the transfer types for each Endpoint in use and also
// if the endpoint wishes to be informed of USB bus resets
@@ -49,7 +49,8 @@ XUD_EpType epTypeTableIn[] = {XUD_EPTYPE_CTL | XUD_STATUS_ENABLE, XUD_EPTYPE_
void XUA_Buffer_lite(chanend c_aud_out, chanend c_feedback, chanend c_aud_in, chanend c_sof, chanend c_aud_ctl, in port p_for_mclk_count, chanend c_aud_host);
[[distributable]]
void AudioHub(server i2s_frame_callback_if i2s, chanend c_aud, client i2c_master_if i2c, client output_gpio_if dac_reset);
void AudioHub(server i2s_frame_callback_if i2s, chanend c_aud, client i2c_master_if ?i2c, client output_gpio_if dac_reset);
void AudioHwConfigure(unsigned samFreq, client i2c_master_if i_i2c);
int main()
{
@@ -73,37 +74,40 @@ int main()
par
{
on tile[0]: {
// Connect master-clock clock-block to clock-block pin
set_clock_src(clk_audio_mclk, p_mclk_in); // Clock clock-block from mclk pin
set_port_clock(p_for_mclk_count, clk_audio_mclk); // Clock the "count" port from the clock block
start_clock(clk_audio_mclk); // Set the clock off running
par {
i2s_frame_master(i_i2s, p_i2s_dac, 1, p_i2s_adc, 1, p_bclk, p_lrclk, p_mclk_in, clk_audio_bclk);
[[distribute]]AudioHub(i_i2s, c_audio, null, i_gpio[0]);
[[distribute]]output_gpio(i_gpio, 1, p_gpio, null);
}
}
on tile[1]:{
// Connect master-clock clock-block to clock-block pin
set_clock_src(clk_usb_mclk, p_mclk_in_usb); // Clock clock-block from mclk pin
set_port_clock(p_for_mclk_count, clk_usb_mclk); // Clock the "count" port from the clock block
start_clock(clk_usb_mclk); // Set the clock off running
par{
i2c_master(i_i2c, 1, p_scl, p_sda, 100);
AudioHwConfigure(DEFAULT_FREQ, i_i2c[0]);
}
par{
// Low level USB device layer core
XUD_Main(c_ep_out, 2, c_ep_in, 3,
c_sof, epTypeTableOut, epTypeTableIn,
null, null, -1 ,
(AUDIO_CLASS == 1) ? XUD_SPEED_FS : XUD_SPEED_HS, XUD_PWR_BUS);
// Endpoint 0 core from lib_xua
// Note, since we are not using many features we pass in null for quite a few params..
XUA_Endpoint0(c_ep_out[0], c_ep_in[0], c_aud_ctl, null, null, null, null);
// Buffering cores - handles audio data to/from EP's and gives/gets data to/from the audio I/O core
XUA_Buffer_lite(c_ep_out[1], c_ep_in[2], c_ep_in[1], c_sof, c_aud_ctl, p_for_mclk_count, c_audio);
i2s_frame_master(i_i2s, p_i2s_dac, 1, p_i2s_adc, 1, p_bclk, p_lrclk, p_mclk_in, clk_audio_bclk);
[[distribute]]AudioHub(i_i2s, c_audio, i_i2c[0], i_gpio[0]);
[[distribute]]output_gpio(i_gpio, 1, p_gpio, null);
}
}
on tile[1]:{
par{
i2c_master(i_i2c, 1, p_scl, p_sda, 100);
}
}
}
}//Tile[1]
}//Top level par
return 0;
}