From 3a74a3863846ab227c236fa17e9295118562a35b Mon Sep 17 00:00:00 2001 From: Ross Owen Date: Fri, 25 Apr 2014 12:28:09 +0100 Subject: [PATCH] Master clock used to clock bit-clock clock-block directly when BCLK==MCLK. This improves I2S timing (esp at 384kHz when MCLK=24.576Mhz..) --- module_usb_audio/ports/audioports.xc | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/module_usb_audio/ports/audioports.xc b/module_usb_audio/ports/audioports.xc index 9e5fcd63..026d9f20 100644 --- a/module_usb_audio/ports/audioports.xc +++ b/module_usb_audio/ports/audioports.xc @@ -65,16 +65,19 @@ unsigned int divide) if (divide == 1) /* e.g. 176.4KHz from 11.2896 */ { configure_port_clock_output(p_bclk, clk_audio_mclk); + + /* Generate bit clock block straight from mclk */ + configure_clock_src(clk_audio_bclk, p_mclk_in); } else { /* bit clock port from master clock clock-clock block */ configure_out_port_no_ready(p_bclk, clk_audio_mclk, 0); + + /* Generate bit clock block from pin */ + configure_clock_src(clk_audio_bclk, p_bclk); } - - /* Generate bit clock block from pin */ - configure_clock_src(clk_audio_bclk, p_bclk); - + if(!isnull(p_lrclk)) { /* Clock LR clock from bit clock-block */