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Added MIN_FREQ define, MAX_FREQ now auto-defined as 192k, Native DSD enabled by default (if DSD enabled)

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This commit is contained in:
Ross Owen
2013-10-23 12:39:48 +01:00
parent d74bd15ed4
commit 538f6f3bf3
3 changed files with 47 additions and 23 deletions
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43
module_usb_audio/devicedefines.h
View File

@@ -29,10 +29,38 @@
#endif #endif
#endif #endif
#if (MAX_FREQ > 96000) #if !defined (DSD_CHANS_DAC)
#define MAX_FREQ_A1 96000 #define DSD_CHANS_DAC 0
#else #else
#define MAX_FREQ_A1 MAX_FREQ #define NATIVE_DSD 1 /* Always enable Native DSD when DSD mode is enabled */
#endif
/* Max supported sample freq for device */
#ifndef MAX_FREQ
#warning MAX_FREQ not defined! Using 192000
#define MAX_FREQ (192000)
#endif
/* Min supported sample freq for device */
#ifndef MIN_FREQ
#warning MIN_FREQ not defined! Using 44100
#define MIN_FREQ (44100)
#endif
#if ((MCLK_44 % MIN_FREQ) == 0)
#define MIN_FREQ_44 MIN_FREQ
#define MIN_FREQ_48 ((48000 * 512)/((44100 * 512)/MIN_FREQ))
#endif
#if ((MCLK_48 % MIN_FREQ) == 0)
#define MIN_FREQ_48 MIN_FREQ
#define MIN_FREQ_44 (((44100*512)/((48000 * 512)/MIN_FREQ))*2)
#endif
#if (MAX_FREQ > 96000)
#define MAX_FREQ_A1 96000
#else
#define MAX_FREQ_A1 MAX_FREQ
#endif #endif
/* For Audio Class 1.0 we always have at most 2 channels */ /* For Audio Class 1.0 we always have at most 2 channels */
@@ -144,16 +172,11 @@
#define SPDIF_TX_INDEX (0) #define SPDIF_TX_INDEX (0)
#endif #endif
/* Max supported freq for device */
#ifndef MAX_FREQ
#warning MAX_FREQ not defined! Using 48000
#define MAX_FREQ (48000)
#endif
/* Default device freq */ /* Default device freq */
#ifndef DEFAULT_FREQ #ifndef DEFAULT_FREQ
#warning DEFAULT not defined! Using MAX_FREQ #warning DEFAULT not defined! Using 48000
#define DEFAULT_FREQ (MAX_FREQ) #define DEFAULT_FREQ (48000)
#endif #endif
/* Master clock defines (in Hz) */ /* Master clock defines (in Hz) */

20
module_usb_audio/endpoint0/audiorequests.xc
View File

@@ -790,10 +790,11 @@ int AudioClassRequests_2(XUD_ep ep0_out, XUD_ep ep0_in, USB_SetupPacket_t &sp, c
{ {
int num_freqs = 0; int num_freqs = 0;
int i = 2; int i = 2;
int currentFreq44 = 44100;
int currentFreq48 = 48000; int currentFreq44 = MIN_FREQ_44;
int currentFreq48 = MIN_FREQ_48;
unsigned maxFreq = MAX_FREQ; unsigned maxFreq = MAX_FREQ;
#if defined (FULL_SPEED_AUDIO_2) #if defined (FULL_SPEED_AUDIO_2)
unsigned usbSpeed; unsigned usbSpeed;
asm("ldw %0, dp[g_curUsbSpeed]" : "=r" (usbSpeed) :); asm("ldw %0, dp[g_curUsbSpeed]" : "=r" (usbSpeed) :);
@@ -803,20 +804,21 @@ int AudioClassRequests_2(XUD_ep ep0_out, XUD_ep ep0_in, USB_SetupPacket_t &sp, c
maxFreq = MAX_FREQ_A1; maxFreq = MAX_FREQ_A1;
} }
#endif #endif
while(1) while(1)
{ {
if(currentFreq48 <= maxFreq) if((currentFreq48 <= maxFreq))
{ {
/* Note i passed byref here */ /* Note i passed byref here */
storeFreq(buffer, i, currentFreq48);
num_freqs++;
currentFreq48*=2;
storeFreq(buffer, i, currentFreq44); storeFreq(buffer, i, currentFreq44);
num_freqs++; num_freqs++;
currentFreq44*=2; currentFreq44*=2;
storeFreq(buffer, i, currentFreq48);
num_freqs++;
currentFreq48*=2;
} }
else if(currentFreq44 <= maxFreq) else if((currentFreq44 <= maxFreq))
{ {
storeFreq(buffer, i, currentFreq44); storeFreq(buffer, i, currentFreq44);
num_freqs++; num_freqs++;

7
module_usb_audio/main.xc
View File

@@ -124,17 +124,17 @@ on tile[0] : in port p_mclk_in2 = PORT_MCLK_IN2;
on tile[AUDIO_IO_CORE] : clock clk_audio_bclk = XS1_CLKBLK_3; /* Bit clock */ on tile[AUDIO_IO_CORE] : clock clk_audio_bclk = XS1_CLKBLK_3; /* Bit clock */
#ifdef SPDIF #ifdef SPDIF
on tile[AUDIO_IO_CORE] : clock clk_mst_spd = XS1_CLKBLK_1; on tile[AUDIO_IO_CORE] : clock clk_mst_spd = XS1_CLKBLK_1;
#endif #endif
/* L Series needs a port to use for USB reset */ /* L Series needs a port to use for USB reset */
#ifdef ARCH_L #ifdef ARCH_L
#ifdef PORT_USB_RESET #ifdef PORT_USB_RESET
/* This define is checked since it could be on a shift reg or similar */ /* This define is checked since it could be on a shift reg or similar */
on tile[0] : out port p_usb_rst = PORT_USB_RESET; on tile[0] : out port p_usb_rst = PORT_USB_RESET;
#endif #endif
/* L Series also needs a clock for this port */ /* L Series also needs a clock for this port */
clock clk = XS1_CLKBLK_4; clock clk = XS1_CLKBLK_4;
#else #else
/* Reset port not required for SU1 due to built in Phy */ /* Reset port not required for SU1 due to built in Phy */
#define p_usb_rst null #define p_usb_rst null
@@ -150,7 +150,6 @@ XUD_EpType epTypeTableOut[EP_CNT_OUT] = { XUD_EPTYPE_CTL | XUD_STATUS_ENABLE,
#ifdef IAP #ifdef IAP
XUD_EPTYPE_BUL | XUD_STATUS_ENABLE /* iAP */ XUD_EPTYPE_BUL | XUD_STATUS_ENABLE /* iAP */
#endif #endif
}; };
XUD_EpType epTypeTableIn[EP_CNT_IN] = { XUD_EPTYPE_CTL | XUD_STATUS_ENABLE, XUD_EpType epTypeTableIn[EP_CNT_IN] = { XUD_EPTYPE_CTL | XUD_STATUS_ENABLE,