Fixes to add X200 support and get X200 audio board running

This commit is contained in:
Ross Owen
2015-03-04 12:06:27 +00:00
parent 26dfbadc36
commit 55dd4834c3
2 changed files with 5 additions and 5 deletions

View File

@@ -116,7 +116,7 @@ on tile[AUDIO_IO_TILE] : port p_mclk_in = PORT_MCLK_IN;
on tile[XUD_TILE] : in port p_for_mclk_count = PORT_MCLK_COUNT; on tile[XUD_TILE] : in port p_for_mclk_count = PORT_MCLK_COUNT;
#ifdef SPDIF #ifdef SPDIF
on tile[AUDIO_IO_TILE] : buffered out port:32 p_spdif_tx = PORT_SPDIF_OUT; on tile[SPDIF_TX_TILE] : buffered out port:32 p_spdif_tx = PORT_SPDIF_OUT;
#endif #endif
#ifdef ADAT_TX #ifdef ADAT_TX
@@ -182,7 +182,7 @@ on tile[XUD_TILE] : out port p_usb_rst = PORT_USB_RESET;
#define p_usb_rst null #define p_usb_rst null
#endif #endif
#if (XUD_SERIES_SUPPORT != XUD_U_SERIES) #if (XUD_SERIES_SUPPORT != XUD_U_SERIES && XUD_SERIES_SUPPORT != XUD_X200_SERIES)
/* L Series also needs a clock block for this port */ /* L Series also needs a clock block for this port */
on tile[XUD_TILE] : clock clk = CLKBLK_USB_RST; on tile[XUD_TILE] : clock clk = CLKBLK_USB_RST;
#else #else
@@ -309,7 +309,7 @@ void usb_audio_core(chanend c_mix_out
/* Attach mclk count port to mclk clock-block (for feedback) */ /* Attach mclk count port to mclk clock-block (for feedback) */
//set_port_clock(p_for_mclk_count, clk_audio_mclk); //set_port_clock(p_for_mclk_count, clk_audio_mclk);
#if(AUDIO_IO_TILE != 0) #if(AUDIO_IO_TILE != XUD_TILE)
set_clock_src(clk_audio_mclk2, p_mclk_in2); set_clock_src(clk_audio_mclk2, p_mclk_in2);
set_port_clock(p_for_mclk_count, clk_audio_mclk2); set_port_clock(p_for_mclk_count, clk_audio_mclk2);
start_clock(clk_audio_mclk2); start_clock(clk_audio_mclk2);

View File

@@ -4,7 +4,7 @@
#include "xud.h" /* XMOS USB Device Layer defines and functions */ #include "xud.h" /* XMOS USB Device Layer defines and functions */
#if (XUD_SERIES_SUPPORT != XUD_U_SERIES) #if ((XUD_SERIES_SUPPORT != XUD_U_SERIES) && (XUD_SERIES_SUPPORT != XUD_X200_SERIES))
/* XUD_L_SERIES and XUD_G_SERIES */ /* XUD_L_SERIES and XUD_G_SERIES */
@@ -45,7 +45,7 @@
/* #define CLKBLK_ADAT_RX XS1_CLKBLK_3 */ /* #define CLKBLK_ADAT_RX XS1_CLKBLK_3 */
/* Note, U-series XUD uses clock blocks 4 and 5 - see XUD_Ports.xc */ /* Note, U-series XUD uses clock blocks 4 and 5 - see XUD_Ports.xc */
#define CLKBLK_FLASHLIB XS1_CLKBLK_5 /* Clock block for use by flash lib */ //#define CLKBLK_FLASHLIB XS1_CLKBLK_5 /* Clock block for use by flash lib */
/* #define CLKBLK_SPDIF_TX XS1_CLKBLK_1 */ /* #define CLKBLK_SPDIF_TX XS1_CLKBLK_1 */
/* #define CLKBLK_MCLK XS1_CLKBLK_2 */ /* #define CLKBLK_MCLK XS1_CLKBLK_2 */