forked from PAWPAW-Mirror/lib_xua
- Rename app_test_i2s_loopback to test_i2s_loopback
- Port test_i2s_loopback from xmostest to pytest and test_support
This commit is contained in:
xross
@@ -1,51 +1,147 @@
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#!/usr/bin/env python
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# Copyright 2018-2021 XMOS LIMITED.
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# This Software is subject to the terms of the XMOS Public Licence: Version 1.
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import xmostest
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import pytest
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import Pyxsim
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from Pyxsim import testers
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import os
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import sys
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def runtest_one_config(env, format, i2s_role, num_chans_in, num_chans_out, sample_rate):
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testlevel = 'smoke'
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resources = xmostest.request_resource('xsim')
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binary = 'app_test_i2s_loopback/bin/{env}_{format}_{i2s_role}_{num_chans_in}in_{num_chans_out}out_{sample_rate}/app_test_i2s_loopback_{env}_{format}_{i2s_role}_{num_chans_in}in_{num_chans_out}out_{sample_rate}.xe'.format(env=env, format=format, i2s_role=i2s_role, num_chans_in=num_chans_in, num_chans_out=num_chans_out, sample_rate=sample_rate)
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tester = xmostest.ComparisonTester(open('pass.expect'),
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'lib_xua',
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'i2s_loopback_sim_tests',
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'i2s_loopback',
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{'env':env,
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'format':format,
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'i2s_role':i2s_role,
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'num_chans_in':num_chans_in,
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'num_chans_out':num_chans_out,
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'sample_rate':sample_rate})
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tester.set_min_testlevel(testlevel)
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loopback_args= '-port tile[0] XS1_PORT_1M 1 0 -port tile[0] XS1_PORT_1I 1 0 ' + \
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'-port tile[0] XS1_PORT_1N 1 0 -port tile[0] XS1_PORT_1J 1 0 ' + \
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'-port tile[0] XS1_PORT_1O 1 0 -port tile[0] XS1_PORT_1K 1 0 ' + \
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'-port tile[0] XS1_PORT_1P 1 0 -port tile[0] XS1_PORT_1L 1 0 ' + \
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'-port tile[0] XS1_PORT_1A 1 0 -port tile[0] XS1_PORT_1F 1 0 '
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if i2s_role == 'slave':
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loopback_args += '-port tile[0] XS1_PORT_1B 1 0 -port tile[0] XS1_PORT_1H 1 0 ' #bclk
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loopback_args += '-port tile[0] XS1_PORT_1C 1 0 -port tile[0] XS1_PORT_1G 1 0 ' #lrclk
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@pytest.fixture()
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def test_file(request):
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return str(request.node.fspath)
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max_cycles = 1500000 #enough to reach the 10 skip + 100 test in sim at 48kHz
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xmostest.run_on_simulator(resources['xsim'], binary, tester=tester, simargs=['--max-cycles', str(max_cycles), '--plugin', 'LoopbackPort.dll', loopback_args])
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def runtest():
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runtest_one_config('simulation', 'i2s', 'master', 2, 2, '48khz')
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runtest_one_config('simulation', 'i2s', 'slave', 2, 2, '48khz')
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def create_if_needed(folder):
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if not os.path.exists(folder):
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os.makedirs(folder)
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return folder
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runtest_one_config('simulation', 'i2s', 'master', 2, 2, '192khz')
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runtest_one_config('simulation', 'i2s', 'slave', 2, 2, '192khz')
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runtest_one_config('simulation', 'i2s', 'master', 8, 8, '48khz')
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runtest_one_config('simulation', 'i2s', 'slave', 8, 8, '48khz')
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def get_sim_args(testname, desc, options):
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sim_args = []
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runtest_one_config('simulation', 'i2s', 'master', 8, 8, '192khz')
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runtest_one_config('simulation', 'i2s', 'slave', 8, 8, '192khz')
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if options.enabletracing:
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log_folder = create_if_needed("logs")
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runtest_one_config('simulation', 'tdm', 'master', 8, 8, '48khz')
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runtest_one_config('simulation', 'tdm', 'slave', 8, 8, '48khz')
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filename = "{log}/xsim_trace_{test}_{desc}".format(
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log=log_folder,
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test=testname,
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desc=desc,
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)
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runtest_one_config('simulation', 'tdm', 'master', 16, 16, '48khz')
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runtest_one_config('simulation', 'tdm', 'slave', 16, 16, '48khz')
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sim_args += [
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"--trace-to",
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"{0}.txt".format(filename),
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"--enable-fnop-tracing",
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]
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vcd_args = "-o {0}.vcd".format(filename)
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vcd_args += (
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" -tile tile[0] -ports -ports-detailed -instructions"
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" -functions -cycles -clock-blocks -pads -cores -usb"
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)
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sim_args += ["--vcd-tracing", vcd_args]
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return sim_args
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def run_on_simulator(xe, simthreads, **kwargs):
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for k in ["do_xe_prebuild", "build_env", "clean_before_build"]:
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if k in kwargs:
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kwargs.pop(k)
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Pyxsim.run_with_pyxsim(xe, simthreads, **kwargs)
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def do_test(pcm_format, i2s_role, channel_count, sample_rate, test_file, capfd, options):
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build_options = []
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output = []
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testname, _ = os.path.splitext(os.path.basename(test_file))
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desc = f"simulation_{pcm_format}_{i2s_role}_{channel_count}in_{channel_count}out_{sample_rate}"
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binary = f"{testname}/bin/{desc}/{testname}_{desc}.xe"
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build_success, _ = Pyxsim._build(
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binary, do_clean=False, build_options=build_options
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)
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if build_success:
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tester = testers.ComparisonTester(
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open("pass.expect"),
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"lib_xua",
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"xua_sim_tests",
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testname,
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{
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"speed": "500MHz",
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"arch": "XS2",
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}, # TODO run tests on XS3 and other core freqs
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)
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loopback_args = (
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"-port tile[0] XS1_PORT_1M 1 0 -port tile[0] XS1_PORT_1I 1 0 "
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+ "-port tile[0] XS1_PORT_1N 1 0 -port tile[0] XS1_PORT_1J 1 0 "
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+ "-port tile[0] XS1_PORT_1O 1 0 -port tile[0] XS1_PORT_1K 1 0 "
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+ "-port tile[0] XS1_PORT_1P 1 0 -port tile[0] XS1_PORT_1L 1 0 "
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+ "-port tile[0] XS1_PORT_1A 1 0 -port tile[0] XS1_PORT_1F 1 0 "
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)
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if i2s_role == "slave":
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loopback_args += (
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"-port tile[0] XS1_PORT_1B 1 0 -port tile[0] XS1_PORT_1H 1 0 " # bclk
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)
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loopback_args += (
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"-port tile[0] XS1_PORT_1C 1 0 -port tile[0] XS1_PORT_1G 1 0 " # lrclk
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)
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max_cycles = 1500000 # enough to reach the 10 skip + 100 test in sim at 48kHz
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simargs = get_sim_args(testname, desc, options)
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simargs = simargs + [
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"--max-cycles",
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str(max_cycles),
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"--plugin",
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"LoopbackPort.dll",
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loopback_args,
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]
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simthreads = []
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run_on_simulator(binary, simthreads, simargs=simargs)
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cap_output, err = capfd.readouterr()
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output.append(cap_output.split("\n"))
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sys.stdout.write("\n")
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results = Pyxsim.run_tester(output, [tester])
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return results
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else:
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print("Build Failed")
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return [False]
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@pytest.mark.parametrize("i2s_role", ["master", "slave"])
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@pytest.mark.parametrize("pcm_format", ["i2s", "tdm"])
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@pytest.mark.parametrize("channel_count", [2, 8, 16])
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@pytest.mark.parametrize("sample_rate", ["48khz", "192khz"])
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def test_i2s_loopback(
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i2s_role, pcm_format, channel_count, sample_rate, test_file, capfd, options
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):
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if pcm_format == "i2s" and channel_count == 16:
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pytest.skip("Invalid parameter combination")
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if pcm_format == "tdm" and channel_count == 2:
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pytest.skip("Invalid parameter combination")
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if pcm_format == "tdm" and sample_rate == "192khz":
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pytest.skip("Invalid parameter combination")
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results = do_test(
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pcm_format, i2s_role, channel_count, sample_rate, test_file, capfd, options
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)
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assert results[0]
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