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Fixed build issue in app_xua_simple due to unsafe mclk port

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xross
2017-11-01 16:23:03 +00:00
parent 8ceec63c5d
commit 99fa8b0442
2 changed files with 8 additions and 4 deletions
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1
examples/app_xua_simple/src/app_xua_simple.xc
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@@ -27,6 +27,7 @@ port p_mclk_in_ = PORT_MCLK_IN;
unsafe unsafe
{ {
/* TODO simplify this */
unsafe port p_mclk_in; /* Audio master clock input */ unsafe port p_mclk_in; /* Audio master clock input */
} }

11
lib_xua/src/core/ports/audioports.xc
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@@ -6,7 +6,7 @@
extern port p_mclk_in; extern unsafe port p_mclk_in;
extern clock clk_audio_mclk; extern clock clk_audio_mclk;
extern clock clk_audio_bclk; extern clock clk_audio_bclk;
@@ -58,9 +58,12 @@ unsigned int divide, unsigned curSamFreq)
#endif #endif
#if defined(__XS2A__) #if defined(__XS2A__)
/* Clock bitclock clock block from master clock pin (divided) */ unsafe
configure_clock_src_divide(clk_audio_bclk, p_mclk_in, (divide/2)); {
configure_port_clock_output(p_bclk, clk_audio_bclk); /* Clock bitclock clock block from master clock pin (divided) */
configure_clock_src_divide(clk_audio_bclk, (port) p_mclk_in, (divide/2));
configure_port_clock_output(p_bclk, clk_audio_bclk);
}
#else #else
/* For a divide of one (i.e. bitclock == master-clock) BClk is set to clock_output mode. /* For a divide of one (i.e. bitclock == master-clock) BClk is set to clock_output mode.
* In this mode it outputs an edge clock on every tick of itsassociated clock_block. * In this mode it outputs an edge clock on every tick of itsassociated clock_block.