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DSD port updates

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This commit is contained in:
Ross Owen
2013-06-28 12:45:31 +01:00
parent 160010acda
commit a081ef00ae
3 changed files with 93 additions and 76 deletions
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79
module_usb_audio/ports/audioports.c
View File

@@ -1,36 +1,38 @@
#include <xccompat.h>
#include <xs1.h>
#define __ASSEMBLER__ // Work around for bug #14118
#include <platform.h>
#undef __ASSEMBLER__
#include "devicedefines.h"
#include "audioports.h"
//#define p_dsd_left p_i2s_dac[0]
//#define p_dsd_right p_bclk
#define p_dsd_clk p_lrclk
//#d
#if 0
#ifndef p_dsd_clk
buffered out port:32 p_dsd_clk = P_DSD_CLK;
#ifdef DSD_OUTPUT
/* Note since DSD ports could be reused for I2S ports we do all the setup manually in C */
#if DSD_CHANS_DAC > 0
port p_dsd_dac[DSD_CHANS_DAC] = {
PORT_DSD_DAC0,
#endif
#if DSD_CHANS_DAC > 1
PORT_DSD_DAC1,
#endif
#if DSD_CHANS_DAC > 2
#error > 2 DSD chans currently not supported
#endif
#if DSD_CHANS_DAC > 0
};
port p_dsd_clk = PORT_DSD_CLK;
#endif
#ifndef p_dsd_left
extern buffered out port:32 p_dsd_left;
#endif
static inline void EnableBufferedPort(port p, unsigned transferWidth)
{
//set_port_use_on(p_dsd_dac[i]);
asm volatile("setc res[%0], %1"::"r"(p), "r"(XS1_SETC_INUSE_ON));
asm volatile("setc res[%0], %1"::"r"(p), "r"(XS1_SETC_BUF_BUFFERS));
asm volatile("settw res[%0], %1"::"r"(p),"r"(transferWidth));
}
#ifndef p_dsd_right
extern buffered out port:32 p_dsd_right;
#endif
#if I2S_WIRES_DAC > 0
#ifndef p_dsd_dac0
on tile[0] : buffered out port:32 p_dsd_dac0 = PORT_DSD_DAC0;
#endif
dsdPorts[0] = PORT_DSD_DAC0;
#endif
#endif
/* C wrapper for ConfigAudioPorts() such that we can mess around with arrays of ports */
void ConfigAudioPortsWrapper(
#if (I2S_CHANS_DAC != 0)
port p_i2s_dac[I2S_WIRES_DAC],
@@ -54,6 +56,32 @@ unsigned int divide, unsigned int dsdMode)
if(dsdMode)
{
/* Make sure the ports are on and buffered - just in case they are not shared with I2S */
for(int i = 0; i< DSD_CHANS_DAC; i++)
{
EnableBufferedPort(p_dsd_dac[i], 32);
}
EnableBufferedPort(p_dsd_clk, 32);
ConfigAudioPorts(
#if (DSD_CHANS_DAC != 0)
p_dsd_dac,
DSD_CHANS_DAC,
#endif
#if (I2S_CHANS_ADC != 0)
p_i2s_adc,
I2S_WIRES_ADC,
#endif
#if (I2S_CHANS_DAC != 0) || (I2S_CHANS_ADC != 0)
#ifndef CODEC_MASTER
0, /* NULL */
p_dsd_clk,
#else
0, /* NULL */
p_dsd_clock,
#endif
#endif
divide);
}
else
@@ -61,9 +89,11 @@ unsigned int divide, unsigned int dsdMode)
ConfigAudioPorts(
#if (I2S_CHANS_DAC != 0)
p_i2s_dac,
I2S_WIRES_DAC,
#endif
#if (I2S_CHANS_ADC != 0)
p_i2s_adc,
I2S_WIRES_ADC,
#endif
#if (I2S_CHANS_DAC != 0) || (I2S_CHANS_ADC != 0)
#ifndef CODEC_MASTER
@@ -77,3 +107,4 @@ unsigned int divide, unsigned int dsdMode)
divide);
}
}
#endif

21
module_usb_audio/ports/audioports.h
View File

@@ -9,20 +9,23 @@ void ConfigAudioPorts_dsd(unsigned int divide);
#ifdef __XC__
void ConfigAudioPorts(
#if (I2S_CHANS_DAC != 0)
buffered out port:32 p_i2s_dac[I2S_WIRES_DAC],
#if (I2S_CHANS_DAC != 0) || (DSD_CHANS_DAC != 0)
buffered out port:32 p_i2s_dac[],
int numDacPorts,
#endif
#if (I2S_CHANS_ADC != 0)
buffered in port:32 p_i2s_adc[I2S_WIRES_ADC],
buffered in port:32 p_i2s_adc[],
int numAdcPorts,
#endif
#if (I2S_CHANS_DAC != 0) || (I2S_CHANS_ADC != 0)
#ifndef CODEC_MASTER
buffered out port:32 p_lrclk,
buffered out port:32 ?p_lrclk,
buffered out port:32 p_bclk,
#else
in port p_lrclk,
in port ?p_lrclk,
in port p_bclk,
#endif
#endif
@@ -30,12 +33,14 @@ void ConfigAudioPorts(
#else
void ConfigAudioPorts(
#if (I2S_CHANS_DAC != 0)
port p_i2s_dac[I2S_WIRES_DAC],
#if (I2S_CHANS_DAC != 0) || (DSD_CHANS_DAC != 0)
port p_i2s_dac[],
int numDacPorts,
#endif
#if (I2S_CHANS_ADC != 0)
port p_i2s_adc[I2S_WIRES_ADC],
port p_i2s_adc[],
int numAdcPorts,
#endif
#if (I2S_CHANS_DAC != 0) || (I2S_CHANS_ADC != 0)

59
module_usb_audio/ports/audioports.xc
View File

@@ -1,54 +1,29 @@
#include <xs1.h>
#include <xccompat.h>
#include <platform.h>
#include "devicedefines.h"
#include "audioports.h"
#ifdef DSD_OUTPUT
#error Building audioports with DSD
#ifndef p_dsd_clk
buffered out port:32 p_dsd_clk = P_DSD_CLK;
#endif
#ifndef p_dsd_left
extern buffered out port:32 p_dsd_left;
#endif
#ifndef p_dsd_right
extern buffered out port:32 p_dsd_right;
#endif
#if I2S_WIRES_DAC > 0
#ifndef p_dsd_dac0
on tile[0] : buffered out port:32 p_dsd_dac0 = PORT_DSD_DAC0;
#endif
dsdPorts[0] = PORT_DSD_DAC0;
#endif
#endif
extern port p_mclk_in;
extern clock clk_audio_mclk;
extern clock clk_audio_bclk;
void ConfigAudioPorts(
#if (I2S_CHANS_DAC != 0)
buffered out port:32 p_i2s_dac[I2S_WIRES_DAC],
// port p_i2s_dac[I2S_WIRES_DAC],
#if (I2S_CHANS_DAC != 0) || (DSD_CHANS_DAC != 0)
buffered out port:32 p_i2s_dac[],
int numPortsDac,
#endif
#if (I2S_CHANS_ADC != 0)
buffered in port:32 p_i2s_adc[I2S_WIRES_ADC],
// port p_i2s_adc[I2S_WIRES_ADC],
buffered in port:32 p_i2s_adc[],
int numPortsAdc,
#endif
#if (I2S_CHANS_DAC != 0) || (I2S_CHANS_ADC != 0)
#ifndef CODEC_MASTER
buffered out port:32 p_lrclk,
buffered out port:32 ?p_lrclk,
buffered out port:32 p_bclk,
//port p_lrclk,
//port p_bclk,
#else
in port p_lrclk,
in port ?p_lrclk,
in port p_bclk,
#endif
#endif
@@ -66,18 +41,21 @@ unsigned int divide)
stop_clock(clk_audio_bclk);
stop_clock(clk_audio_mclk);
if(!isnull(p_lrclk))
{
clearbuf(p_lrclk);
}
clearbuf(p_bclk);
#if (I2S_CHANS_ADC != 0)
for(int i = 0; i < I2S_WIRES_ADC; i++)
for(int i = 0; i < numPortsAdc; i++)
{
clearbuf(p_i2s_adc[i]);
}
#endif
#if (I2S_CHANS_DAC != 0)
for(int i = 0; i < I2S_WIRES_DAC; i++)
for(int i = 0; i < numPortsDac; i++)
{
clearbuf(p_i2s_dac[i]);
}
@@ -105,10 +83,15 @@ unsigned int divide)
/* Generate bit clock block from pin */
configure_clock_src(clk_audio_bclk, p_bclk);
if(!isnull(p_lrclk))
{
/* Clock LR clock from bit clock-block */
configure_out_port_no_ready(p_lrclk, clk_audio_bclk, 0);
}
#if (I2S_CHANS_DAC != 0)
/* Clock I2S output data ports from clock block */
for(int i = 0; i < I2S_WIRES_DAC; i++)
for(int i = 0; i < numPortsDac; i++)
{
configure_out_port_no_ready(p_i2s_dac[i], clk_audio_bclk, 0);
}
@@ -116,14 +99,12 @@ unsigned int divide)
#if (I2S_CHANS_ADC != 0)
/* Clock I2S input data ports from clock block */
for(int i = 0; i < I2S_WIRES_ADC; i++)
for(int i = 0; i < numPortsAdc; i++)
{
configure_in_port_no_ready(p_i2s_adc[i], clk_audio_bclk);
}
#endif
/* Clock LR clock from bit clock-block */
configure_out_port_no_ready(p_lrclk, clk_audio_bclk, 0);
/* Start clock blocks ticking */
start_clock(clk_audio_mclk);