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PDM microphone clock divide now based MCLK defines (previously hard-coded)

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This commit is contained in:
Ross Owen
2016-10-05 12:56:00 +01:00
parent 2a36c3722a
commit ad791c2806
1 changed files with 13 additions and 2 deletions
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15
module_usb_audio/pdm_mics/pdm_mic.xc
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@@ -12,6 +12,7 @@
#include <string.h> #include <string.h>
#include <xclib.h> #include <xclib.h>
#include <stdint.h> #include <stdint.h>
#include <assert.h>
#include "mic_array.h" #include "mic_array.h"
#include "xua_pdm_mic.h" #include "xua_pdm_mic.h"
@@ -181,12 +182,22 @@ void pdm_buffer(streaming chanend c_ds_output[2], chanend c_audio)
#error MAX_FREQ > 48000 NOT CURRENTLY SUPPORTED #error MAX_FREQ > 48000 NOT CURRENTLY SUPPORTED
#endif #endif
#include "print.h"
void pdm_mic(streaming chanend c_ds_output[2]) void pdm_mic(streaming chanend c_ds_output[2])
{ {
streaming chan c_4x_pdm_mic_0, c_4x_pdm_mic_1; streaming chan c_4x_pdm_mic_0, c_4x_pdm_mic_1;
/* Note, this divide should be based on master clock freq */ /* Mics expect a clock in the 3Mhz range, calculate the divide based on mclk */
configure_clock_src_divide(pdmclk, p_mclk, 2); /* e.g. For a 48kHz range mclk we expect a 3072000Hz mic clock */
/* e.g. For a 44.1kHz range mclk we expect a 2822400Hz mic clock */
/* Note, codebase currently does not handle a different divide for each clock */
assert((MCLK_48 % 3072000) == (MCLK_441 % 2822400));
unsigned micDiv = MCLK_48/3072000;
configure_clock_src_divide(pdmclk, p_mclk, micDiv/2);
configure_port_clock_output(p_pdm_clk, pdmclk); configure_port_clock_output(p_pdm_clk, pdmclk);
configure_in_port(p_pdm_mics, pdmclk); configure_in_port(p_pdm_mics, pdmclk);
start_clock(pdmclk); start_clock(pdmclk);