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Remove XS1 support and tidy up white space

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mbanth
2021-06-16 14:46:02 +01:00
parent a3617a641f
commit ada99bd1d9
1 changed files with 9 additions and 10 deletions
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11
lib_xua/src/core/main.xc
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@@ -198,9 +198,9 @@ in port p_pdm_mclk = PORT_PDM_MCLK;
#if(XUD_SERIES_SUPPORT == XUD_L_SERIES) && (ADAT_RX) #if (defined(__XS2A__) && (ADAT_RX))
/* Cannot use default clock (CLKBLK_REF) for ADAT RX since it is tied to the /* Cannot use default clock (CLKBLK_REF) for ADAT RX since it is tied to the
60MHz USB clock on G/L series parts. */ 60MHz USB clock on XS2 processors. */
on tile[XUD_TILE] : clock clk_adat_rx = CLKBLK_ADAT_RX; on tile[XUD_TILE] : clock clk_adat_rx = CLKBLK_ADAT_RX;
#endif #endif
@@ -216,11 +216,10 @@ on tile[AUDIO_IO_TILE] : clock clk_audio_bclk = CLKBLK_I2S_BIT; /*
/* L/G Series needs a port to use for USB reset */ /* L/G Series needs a port to use for USB reset */
#if (XUD_SERIES_SUPPORT != XUD_U_SERIES) && defined(PORT_USB_RESET) #if ((defined(__XS2A__) || defined (__XS3A__)) && defined(PORT_USB_RESET))
/* This define is checked since it could be on a shift reg or similar */ /* This define is checked since it could be on a shift reg or similar */
on tile[XUD_TILE] : out port p_usb_rst = PORT_USB_RESET; on tile[XUD_TILE] : out port p_usb_rst = PORT_USB_RESET;
#else #else
/* Reset port not required for U series due to built in Phy */
#define p_usb_rst null #define p_usb_rst null
#endif #endif
@@ -726,8 +725,8 @@ int main()
{ {
set_thread_fast_mode_on(); set_thread_fast_mode_on();
#if(XUD_SERIES_SUPPORT == XUD_L_SERIES) #if defined(__XS2A__)
/* Can't use REF clock on L-series as this is usb clock */ /* Can't use REF clock as this is usb clock */
set_port_clock(p_adat_rx, clk_adat_rx); set_port_clock(p_adat_rx, clk_adat_rx);
start_clock(clk_adat_rx); start_clock(clk_adat_rx);
#endif #endif