From b2660cf04e4705b99d027061d7576afc03d7124c Mon Sep 17 00:00:00 2001 From: Ross Owen Date: Thu, 23 Jan 2014 17:59:26 +0000 Subject: [PATCH] Another crack the the master mode LR swap issue. --- module_usb_audio/audio.xc | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/module_usb_audio/audio.xc b/module_usb_audio/audio.xc index 6409493d..0b81d2de 100755 --- a/module_usb_audio/audio.xc +++ b/module_usb_audio/audio.xc @@ -351,23 +351,13 @@ static inline void doI2SClocks(unsigned divide) #else /* ifndef CODEC_MASTER */ /* Wait for LRCLK edge */ - p_lrclk when pinseq(1) :> void; p_lrclk when pinseq(0) :> void; p_lrclk when pinseq(1) :> void; p_lrclk when pinseq(0) :> void; - p_lrclk when pinseq(1) :> void @ tmp; - tmp += 96; - -#if (I2S_CHANS_ADC != 0) -#pragma loop unroll - for(int i = 0; i < I2S_WIRES_ADC; i++) - { - asm("setpt res[%0], %1"::"r"(p_i2s_adc[i]),"r"(tmp)); - } -#endif - + p_lrclk when pinseq(1) :> void; + p_lrclk when pinseq(0) :> void @ tmp; + tmp+=95; #if (I2S_CHANS_DAC != 0) - tmp+=33; #pragma loop unroll for(int i = 0; i < I2S_WIRES_DAC; i++) { @@ -375,6 +365,15 @@ static inline void doI2SClocks(unsigned divide) } #endif +#if (I2S_CHANS_ADC != 0) + tmp += 33; +#pragma loop unroll + for(int i = 0; i < I2S_WIRES_ADC; i++) + { + asm("setpt res[%0], %1"::"r"(p_i2s_adc[i]),"r"(tmp)); + } +#endif + /* TODO In master mode, the i/o loop assumes L/RCLK = 32bit clocks. We should check this every interation * and resync if we got a bclk glitch */