laiyp/lib_xua
1
0
Fork 0
forked from PAWPAW-Mirror/lib_xua
Code Pull Requests Activity

DSD freq to audiohwconfig() tidyup and generic divide calc

Browse Source
This commit is contained in:
Ross Owen
2013-10-23 12:29:11 +01:00
parent 6c5253abb0
commit d74bd15ed4
1 changed files with 30 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

33
module_usb_audio/audio.xc
View File

@@ -56,6 +56,7 @@ extern in port p_bclk;
unsigned dsdMode = 0; unsigned dsdMode = 0;
#if (DSD_CHANS_DAC != 0) #if (DSD_CHANS_DAC != 0)
/* DoP defines */
#define DSD_MARKER_1 0xFA #define DSD_MARKER_1 0xFA
#define DSD_MARKER_2 0x05 #define DSD_MARKER_2 0x05
#define DSD_MARKER_XOR 0xFF #define DSD_MARKER_XOR 0xFF
@@ -420,6 +421,7 @@ extern void device_reboot(void);
switch (divide) switch (divide)
{ {
case 8: case 8:
/* Output DSD data to ports then 32 clocks */
asm volatile("out res[%0], %1"::"r"(p_dsd_dac[0]),"r"(dsdSample_l)); asm volatile("out res[%0], %1"::"r"(p_dsd_dac[0]),"r"(dsdSample_l));
asm volatile("out res[%0], %1"::"r"(p_dsd_dac[1]),"r"(dsdSample_r)); asm volatile("out res[%0], %1"::"r"(p_dsd_dac[1]),"r"(dsdSample_r));
p_dsd_clk <: 0xF0F0F0F0; p_dsd_clk <: 0xF0F0F0F0;
@@ -601,9 +603,9 @@ extern void device_reboot(void);
#endif #endif
#if defined(SPDIF) && (NUM_USB_CHAN_OUT > 0) #if defined(SPDIF) && (NUM_USB_CHAN_OUT > 0)
outuint(c_spd_out, samplesOut[SPDIF_TX_INDEX]); /* Forward sample to SPDIF txt thread */ outuint(c_spd_out, samplesOut[SPDIF_TX_INDEX]); /* Forward sample to S/PDIF Tx thread */
sample = samplesOut[SPDIF_TX_INDEX + 1]; sample = samplesOut[SPDIF_TX_INDEX + 1];
outuint(c_spd_out, sample); /* Forward sample to SPDIF txt thread */ outuint(c_spd_out, sample); /* Forward sample to S/PDIF Tx thread */
#ifdef RAMP_CHECK #ifdef RAMP_CHECK
sample >>= 8; sample >>= 8;
if (started<10000) { if (started<10000) {
@@ -853,22 +855,17 @@ void audio(chanend c_mix_out, chanend ?c_dig_rx, chanend ?c_config, chanend ?c)
SpdifTransmitPortConfig(p_spdif_tx, clk_mst_spd, p_mclk_in); SpdifTransmitPortConfig(p_spdif_tx, clk_mst_spd, p_mclk_in);
#endif #endif
/* Initialise master clock generation */
//ClockingInit(c_config);
/* Perform required CODEC/ADC/DAC initialisation */ /* Perform required CODEC/ADC/DAC initialisation */
AudioHwInit(c_config); AudioHwInit(c_config);
while(1) while(1)
{ {
/* Calculate what master clock we should be using */ /* Calculate what master clock we should be using */
if ((curSamFreq % 22050) == 0) if ((MCLK_441 % curSamFreq) == 0)
{ {
mClk = MCLK_441; mClk = MCLK_441;
} }
else if ((curSamFreq % 24000) == 0) else if ((MCLK_48 % curSamFreq) == 0)
{ {
mClk = MCLK_48; mClk = MCLK_48;
} }
@@ -879,6 +876,7 @@ void audio(chanend c_mix_out, chanend ?c_dig_rx, chanend ?c_config, chanend ?c)
/* I2S has 32 bits per sample. *2 as 2 channels */ /* I2S has 32 bits per sample. *2 as 2 channels */
unsigned numBits = 64; unsigned numBits = 64;
#if (DSD_CHANS_DAC > 0)
if(dsdMode == DSD_MODE_DOP) if(dsdMode == DSD_MODE_DOP)
{ {
/* DoP we receive in 16bit chunks */ /* DoP we receive in 16bit chunks */
@@ -889,6 +887,7 @@ void audio(chanend c_mix_out, chanend ?c_dig_rx, chanend ?c_config, chanend ?c)
/* DSD native we receive in 32bit chunks */ /* DSD native we receive in 32bit chunks */
numBits = 32; numBits = 32;
} }
#endif
divide = mClk / ( curSamFreq * numBits ); divide = mClk / ( curSamFreq * numBits );
} }
@@ -936,8 +935,22 @@ void audio(chanend c_mix_out, chanend ?c_dig_rx, chanend ?c_config, chanend ?c)
#endif #endif
{
unsigned curFreq = curSamFreq;
#if (DSD_CHANS_DAC > 0)
/* Make AudioHwConfig() implementation a little more user friendly in DSD mode...*/
if(dsdMode == DSD_MODE_NATIVE)
{
curFreq *= 32;
}
else if(dsdMode == DSD_MODE_DOP)
{
curFreq *= 16;
}
#endif
/* Configure Clocking/CODEC/DAC/ADC for SampleFreq/MClk */ /* Configure Clocking/CODEC/DAC/ADC for SampleFreq/MClk */
AudioHwConfig(curSamFreq, mClk, c_config, dsdMode); AudioHwConfig(curFreq, mClk, c_config, dsdMode);
}
if(!firstRun) if(!firstRun)
{ {