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Attempt to fix up CODEC_MASTER output LR swap (introduced when input init made more robust)

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This commit is contained in:
Ross Owen
2014-01-23 12:37:25 +00:00
parent 2b536a00da
commit ede82cd818
1 changed files with 50 additions and 55 deletions
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33
module_usb_audio/audio.xc
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@@ -278,14 +278,13 @@ static inline void doI2SClocks(unsigned divide)
} }
#ifndef CODEC_MASTER #ifndef CODEC_MASTER
/* b_clk must start high */
p_bclk <: 0x80000000;
sync(p_bclk);
#if (DSD_CHANS_DAC > 0) #if (DSD_CHANS_DAC > 0)
if(dsdMode == DSD_MODE_OFF) if(dsdMode == DSD_MODE_OFF)
{ {
#endif #endif
/* b_clk must start high */
p_bclk <: 0x80000000;
sync(p_bclk);
/* Clear I2S port buffers */ /* Clear I2S port buffers */
clearbuf(p_lrclk); clearbuf(p_lrclk);
@@ -302,13 +301,12 @@ static inline void doI2SClocks(unsigned divide)
clearbuf(p_i2s_adc[i]); clearbuf(p_i2s_adc[i]);
} }
#endif #endif
if(divide == 1) if(divide == 1)
{ {
p_lrclk <: 0 @ tmp; p_lrclk <: 0 @ tmp;
tmp += 100; tmp += 100;
/* Since BCLK is free-running, setup outputs/inputs at a know point in the future */ /* Since BCLK is free-running, setup outputs/inputs at a known point in the future */
#if (I2S_CHANS_DAC != 0) #if (I2S_CHANS_DAC != 0)
#pragma loop unroll #pragma loop unroll
for(int i = 0; i < I2S_WIRES_DAC; i++) for(int i = 0; i < I2S_WIRES_DAC; i++)
@@ -323,12 +321,9 @@ static inline void doI2SClocks(unsigned divide)
#if (I2S_CHANS_ADC != 0) #if (I2S_CHANS_ADC != 0)
for(int i = 0; i < I2S_WIRES_ADC; i++) for(int i = 0; i < I2S_WIRES_ADC; i++)
{ {
//p_i2s_adc[0] @ (tmp - 1) :> void;
asm("setpt res[%0], %1"::"r"(p_i2s_adc[i]),"r"(tmp-1)); asm("setpt res[%0], %1"::"r"(p_i2s_adc[i]),"r"(tmp-1));
clearbuf(p_i2s_adc[i]);
} }
#endif #endif
} }
else else
{ {
@@ -341,8 +336,6 @@ static inline void doI2SClocks(unsigned divide)
p_i2s_dac[i] <: 0; p_i2s_dac[i] <: 0;
} }
#endif #endif
p_lrclk <: 0x7FFFFFFF; p_lrclk <: 0x7FFFFFFF;
doI2SClocks(divide); doI2SClocks(divide);
@@ -363,9 +356,18 @@ static inline void doI2SClocks(unsigned divide)
p_lrclk when pinseq(1) :> void; p_lrclk when pinseq(1) :> void;
p_lrclk when pinseq(0) :> void; p_lrclk when pinseq(0) :> void;
p_lrclk when pinseq(1) :> void @ tmp; p_lrclk when pinseq(1) :> void @ tmp;
tmp += 97; tmp += 96;
#if (I2S_CHANS_ADC != 0)
#pragma loop unroll
for(int i = 0; i < I2S_WIRES_ADC; i++)
{
asm("setpt res[%0], %1"::"r"(p_i2s_adc[i]),"r"(tmp));
}
#endif
#if (I2S_CHANS_DAC != 0) #if (I2S_CHANS_DAC != 0)
tmp+=33;
#pragma loop unroll #pragma loop unroll
for(int i = 0; i < I2S_WIRES_DAC; i++) for(int i = 0; i < I2S_WIRES_DAC; i++)
{ {
@@ -373,13 +375,6 @@ static inline void doI2SClocks(unsigned divide)
} }
#endif #endif
#pragma loop unroll
for(int i = 0; i < I2S_WIRES_ADC; i++)
{
asm("setpt res[%0], %1"::"r"(p_i2s_adc[i]),"r"(tmp-1));
clearbuf(p_i2s_adc[i]);
}
/* TODO In master mode, the i/o loop assumes L/RCLK = 32bit clocks. We should check this every interation /* TODO In master mode, the i/o loop assumes L/RCLK = 32bit clocks. We should check this every interation
* and resync if we got a bclk glitch */ * and resync if we got a bclk glitch */